How to do the timing constraint?

[Altera_Forum]

Hi, 

 Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing?  for the set_input_delay and the set_output_delay,what time relation does it tell the FPGA?

[Altera_Forum]

First, that ODDR module on fp1_co is not needed. 

Second, you should also use a PLL on FPGA2 if possible.  You need to set I/O constrains on the two FPGAs as normal.  In the case of FPGA1, this means creating a derived clock on the fp1_co port and setting the output delays referenced on that clock. In the case of FPGA2, you create a base clock on fp2_ci and set the input delays referenced to that clock.  The trick is that you need to keep the following relationship: fp1_max_output_delay + fp2_max_input_delay = clock period fp1_min_output_delay + fp2_min_input_delay = 0  This will be an iterative process. I'd start by with fp1_max_output_delay = fp2_max_output_delay = clock_period/2 and fp1_min_output_delay = fp2_min_input_delay = 0 and see what I get and then adjust as needed.

[Altera_Forum]

--- Quote Start ---  First, that ODDR module on fp1_co is not needed. Second, you should also use a PLL on FPGA2 if possible.  You need to set I/O constrains on the two FPGAs as normal.  In the case of FPGA1, this means creating a derived clock on the fp1_co port and setting the output delays referenced on that clock. In the case of FPGA2, you create a base clock on fp2_ci and set the input delays referenced to that clock.  The trick is that you need to keep the following relationship: fp1_max_output_delay + fp2_max_input_delay = clock period fp1_min_output_delay + fp2_min_input_delay = 0  This will be an iterative process. I'd start by with fp1_max_output_delay = fp2_max_output_delay = clock_period/2 and fp1_min_output_delay = fp2_min_input_delay = 0 and see what I get and then adjust as needed.  --- Quote End ---    Thank you for your reply.And I still have some questions to ask. 1、If I don't use the ODDR module on fp1_co,how do I let the output delay be as same as possible between fp1_co and fp1_do relative to clk1? Or rather that it is unimportant. 2、Is it more better to use PLL on FPGA2?How does the FPGA shift the clock or the data to reach better timing? 3、for set_output_delay(max),which time in TdelayX(X=1~5) does it tell the FPGA1?And How are the TdelayX(X=1~5) applied in Atera FPGA design? 4、for set_output_delay(min),which time in TdelayX(X=1~5) does it tell the FPGA1?And How are the TdelayX(X=1~5) applied in Atera FPGA design? 5、for set_input_delay(max),which time in TdelayX(X=6~9) does it tell the FPGA2?And How are the TdelayX(X=6~9) applied in Atera FPGA design? 6、for set_input_delay(min),which time in TdelayX(X=6~9) does it tell the FPGA2?And How are the TdelayX(X=6~9) applied in Atera FPGA design? 7、How do you confirm whether your timing constraint is the best?by post_sim? or by other way?

[Altera_Forum]

--- Quote Start ---  Hi,  Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing?  for the set_input_delay and the set_output_delay,what time relation does it tell the FPGA?  --- Quote End ---    Using DDR and PLL may not be required in your case but you can keep your design as such then I will do the following: The fpga1 can send data and clk aligned readily and all you need is set max and min output delay to zero implying there is no tSU/tH requirement so the fitter maintains the data clock alignment. At fpga2 assume min tCO = -2ns & max tCO = +2ns then set max input delay to about +2ns and min delay to -2ns then the fitter will try avoid the edge area and hopefully centre data away from clock edges. Only if it fails then you can use PLL here.

[Altera_Forum]

caobaiyu, 

1. Trying to manually adjust delays by adding modules to your design is, generally, a bad idea for bunch of reasons: tools tend to optimize those things away or change the way they're placed. And of course, you have process/voltage/temperature variations. The best way is simply to correctly constrain your design and let the tools do their job.  2. There's a (fairly big) delay between the clock delivered to the FPGA pin and the clock delivered to the flip-flops inside the FPGA, caused by the FPGA clock distribution tree. The PLL can compensate this delay by using the clock delayed by the clock tree as feedback clock. This will cause the clock delivered to the flip-flops to be phase aligned with the clock at the FPGA input pin.  Input/Output delays tell the tools about the delays/requirements of the system that surrounds the FPGA. 3: set_output_delay -min xx -clock clk [get_ports fp1_do] tells the tools that, after leaving the FPGA1 pins, fp1_do will be delayed by a minimum of xx ns and then be captured at the rising edge of clk 4: set_output_delay -max XX -clock clk [get_ports fp1_do] does an equivalent thing Put in another way, it's telling the tools that fp1_do is going to flip-flops which operate on the rising edge of clk and have a tSU of XX ns and a tH of -xx ns.  5,6: set_input_delay -min yy -clock clk [get_ports fp2_di] tells the tools that fp1_di will have a minimum delay of yy ns. Equivalent thing for max. Again, put in another way, it's telling the tools that fp2_di is produced by flip-flops operating on the rising edge of clk and have min_tCO of yy ns and max tCO of YY ns.  In case of doubt, draw a timing diagram.  The tools will then take this information into account and try to optimize the design inside the FPGAs to make sure that all timing requirements are respected.  7. If your constrains meet the relationship I wrote above and TimeQuest says timing requirements are met, then it's OK. You can then try to look at the I/O timings slack in both FPGAs. If one FPGA has large slacks and the other small ones, maybe you should change the constrains a bit to improve it.

[Altera_Forum]

--- Quote Start ---  Using DDR and PLL may not be required in your case but you can keep your design as such then I will do the following: The fpga1 can send data and clk aligned readily and all you need is set max and min output delay to zero implying there is no tSU/tH requirement so the fitter maintains the data clock alignment. At fpga2 assume min tCO = -2ns & max tCO = +2ns then set max input delay to about +2ns and min delay to -2ns then the fitter will try avoid the edge area and hopefully centre data away from clock edges. Only if it fails then you can use PLL here.  --- Quote End ---    Thank you for your reply.And It seems that your timing constraint doesn't satisfy the following relationship mentioned by rbugalho. fp1_max_output_delay + fp2_max_input_delay = clock period fp1_min_output_delay + fp2_min_input_delay = 0 So you have diffrent thought about that?

[Altera_Forum]

--- Quote Start ---  caobaiyu, 1. Trying to manually adjust delays by adding modules to your design is, generally, a bad idea for bunch of reasons: tools tend to optimize those things away or change the way they're placed. And of course, you have process/voltage/temperature variations. The best way is simply to correctly constrain your design and let the tools do their job.  2. There's a (fairly big) delay between the clock delivered to the FPGA pin and the clock delivered to the flip-flops inside the FPGA, caused by the FPGA clock distribution tree. The PLL can compensate this delay by using the clock delayed by the clock tree as feedback clock. This will cause the clock delivered to the flip-flops to be phase aligned with the clock at the FPGA input pin.  Input/Output delays tell the tools about the delays/requirements of the system that surrounds the FPGA. 3: set_output_delay -min xx -clock clk [get_ports fp1_do] tells the tools that, after leaving the FPGA1 pins, fp1_do will be delayed by a minimum of xx ns and then be captured at the rising edge of clk 4: set_output_delay -max XX -clock clk [get_ports fp1_do] does an equivalent thing Put in another way, it's telling the tools that fp1_do is going to flip-flops which operate on the rising edge of clk and have a tSU of XX ns and a tH of -xx ns.  5,6: set_input_delay -min yy -clock clk [get_ports fp2_di] tells the tools that fp1_di will have a minimum delay of yy ns. Equivalent thing for max. Again, put in another way, it's telling the tools that fp2_di is produced by flip-flops operating on the rising edge of clk and have min_tCO of yy ns and max tCO of YY ns.  In case of doubt, draw a timing diagram.  The tools will then take this information into account and try to optimize the design inside the FPGAs to make sure that all timing requirements are respected.  7. If your constrains meet the relationship I wrote above and TimeQuest says timing requirements are met, then it's OK. You can then try to look at the I/O timings slack in both FPGAs. If one FPGA has large slacks and the other small ones, maybe you should change the constrains a bit to improve it.  --- Quote End ---    Thank you for your replay. by what you mentioned,so usually we first assume a value to tSU/tH or max tCO/min_tCO,and then calculate another. for example, set fp2_tsu 2.250 set fp2_th 0.250 set fp1_max_tco [expr 15.625 - $fp2_tsu] set fp1_min_tco [expr $fp2_th]  FPGA1: set_output_delay -clock fp1_co -max [expr $fp2_tsu] [get_ports fp1_do[*]] -add_delay set_output_delay -clock fp1_co -min [expr -$fp2_th] [get_ports fp1_do[*]] -add_delay set_output_delay -clock fp1_co -max [expr $fp2_tsu] -clock_fall [get_ports fp1_do[*]] -add_delay set_output_delay -clock fp1_co -min [expr -$fp2_th] -clock_fall [get_ports fp1_do[*]] -add_delay  FPGA2: set_input_delay -clock fp2_ci -max [expr $fp1_max_tco] [get_ports {fp2_di[*]}] -add_delay set_input_delay -clock fp2_ci -min [expr $fp1_min_tco] [get_ports {fp2_di[*]}] -add_delay set_input_delay -clock fp2_ci -max [expr $fp1_max_tco] -clock_fall [get_ports {fp2_di[*]}] -add_delay set_input_delay -clock fp2_ci -min [expr $fp1_min_tco] -clock_fall [get_ports {fp2_di[*]}] -add_delay  Then see the timing constraint report and adjust the value of tSU/tH or max tCO/min_tCO by the slack value. Right? How to decide what is the assumed value?or it may be any value.

[Altera_Forum]

More generally, the rule would be 

fp1_max_output_delay + fp2_max_input_delay >= clock period fp1_min_input_delay + fp2_min_input_delay <= 0  But using equality gives you the most slack.  So, kaz suggestion meets this requirement for the min delays but not for the max. Regarding max delays, kaz suggested to tell FPGA1 that tSU is zero and then to tell FPGA2 max tCO is 2 ns. But, in fact, by telling FPGA1 that tSU is zero, the fitter may produce a design with a tCO of up to 1 clock period. Vice versa, by telling FPGA2 that max tCO is 2, the fitter may produce a design which has a tSU of clock period - 2 ns.  It will be an iterative process. I'd start with zero for fp2_tH and half clock period for fp2_tSU and see what I get.  (something broked with post editing...)

[Altera_Forum]

--- Quote Start ---    Regarding max delays, kaz suggested to tell FPGA1 that tSU is zero and then to tell FPGA2 max tCO is 2 ns. But, in fact, by telling FPGA1 that tSU is zero, the fitter may produce a design with a tCO of up to 1 clock period. Vice versa, by telling FPGA2 that max tCO is 2, the fitter may produce a design which has a tSU of clock period - 2 ns.   --- Quote End ---    Thanks rbugalho for the contributions, however I just run the tool on a tiny project of a PLL plus output data and output clock aligned through DDR outputs. Here are some results of clk/data alignment figures against my random set output delay figures:   clk_out dout io timing set_output_delay: 0/0 0/0 (max/min) pass tCO achieved 1.922 1.937 ns set_output_delay: 0/0 +2/-2 (max/min) fail tCO achieved 1.973 1.942 ns set_output_delay: +3/-3 +5,-2 (max/min) fail tCO achieved 1.973 1.942 i.e. no change   My own observation is that the tool does not read set delays figures as absolute mathematical targets to achieve... not at all. Neither it reports failure if these particular figures are not achieved. Instead it reports on failling paths based on thes figures.  The tool has limited delay graininess and delay limits. It reads delay figures as information to achieve best it can.  In the above example data and clock are aligned well and that is what the DDR design is for. When I enter delay figures then the change is trivial yet timing failure was reported in case2 and 3 because of the information entered. The tool did not want to alter the clk/data relation that much.  As a side note: A user can easily pass io timing by entering wrong figures (false pass) or the reverse get false failure.

[Altera_Forum]

If you set a max output delay of zero (external tSU of zero), you're not asking the tool to generate a tCO of zero, nor a tCO of 1 clock period.You're telling the tool any tCO below 1 clock period is good and the tool will try to achieve that, with minimum effort.In your example, the minimum effort solution for your design has a tCO of 15 ps, which meets the requirement by a mile.But, if by some fluke, the minimum effort solution had a tCO of 3 ns or 10 ns, then that's what you'd get. It still meets the requirement and you'd still get a pass from TimeQuest.Which is not good, since for the other FPGA, you're telling the tool the max tCO is has to deal with is 2 ns.(can't format my post now...)

[Altera_Forum]

--- Quote Start ---  If you set a max output delay of zero (external tSU of zero), you're not asking the tool to generate a tCO of zero, nor a tCO of 1 clock period.You're telling the tool any tCO below 1 clock period is good and the tool will try to achieve that, with minimum effort.In your example, the minimum effort solution for your design has a tCO of 15 ps, which meets the requirement by a mile.But, if by some fluke, the minimum effort solution had a tCO of 3 ns or 10 ns, then that's what you'd get. It still meets the requirement and you'd still get a pass from TimeQuest.Which is not good, since for the other FPGA, you're telling the tool the max tCO is has to deal with is 2 ns.(can't format my post now...)  --- Quote End ---    Correct. A set_output_delay of zero means no requirements at all and the tool is free. The user must then observe the actual tCO produced. In this case and due to DDR output of data and clock I expect very small tCO (data and clock aligned as is the test I did).  Once the user controls alignment of fpga1 outputs then he can deal with fpga2 input stage. Thus the control of timing is shared between both fpgas.

[Altera_Forum]

That's a labour intensive and/or error prone process. 

Every time you run a new fit for FPGA1, you need to re-check the tCOs you got. If they're different from the tCOs you've constrained FPGA2 with, then you need to manually check and, if needed, update FPGA2's constrains and run a new fit  If instead you specify reasonable constraints for both FPGAs that meet the conditions I wrote before, then you can just trust TQ to fail your design if something goes wrong. And if those constrains are well balanced between the FPGAs, you'll probably never have to change them again.

[Altera_Forum]

--- Quote Start ---  That's a labour intensive and/or error prone process. Every time you run a new fit for FPGA1, you need to re-check the tCOs you got. If they're different from the tCOs you've constrained FPGA2 with, then you need to manually check and, if needed, update FPGA2's constrains and run a new fit  If instead you specify reasonable constraints for both FPGAs that meet the conditions I wrote before, then you can just trust TQ to fail your design if something goes wrong. And if those constrains are well balanced between the FPGAs, you'll probably never have to change them again.  --- Quote End ---    You are right in principle but I don't think so practically with tool's behaviour because DDR takes care of alignment. Moreover remember you may set delay figure to some nonzero and then you target some close range of tCOs as 15 ps between data and its clock. I view setting delay to zero is a constraint by itself rather than deconstraint.   The second fpga is given a false wider margin of tCO and that is why I suggested +/- 2ns instead of actual +15ps. you can further widen that up if timing can pass  Your approach is also worth trying i.e. share the delay figures from start and see if timing passes on both fpgas instead of using my false figures.

[Altera_Forum]

I have used this methodology in the past (that's why I know it) and it does work. 

And of course, if you apply this methodology to your example design, you're going to get exactly the same result. The minimum solution the fitter gave you, with a 15 ps tCO, will also meet a 0/7.8125 min/max output delay constraint by a mile.  As you may have noticed, I really dislike not having solid time constrains. Independently of weather a unconstrained design meets timing requirements by a mile or I have to manually place bits of logic to meet timing, I _always_ try to have solid constraints at my starting point.

[Altera_Forum]

Thank you for your reply. 

And I did the following test. for example, set fp2_tsu 7.8125 set fp2_th 0.0000 set fp1_max_tco [expr 15.625 - $fp2_tsu] set fp1_min_tco [expr $fp2_th]  FPGA1: set_output_delay -clock fp1_co -max [expr $fp2_tsu] [get_ports fp1_do[*]] -add_delay set_output_delay -clock fp1_co -min [expr -$fp2_th] [get_ports fp1_do[*]] -add_delay set_output_delay -clock fp1_co -max [expr $fp2_tsu] -clock_fall [get_ports fp1_do[*]] -add_delay set_output_delay -clock fp1_co -min [expr -$fp2_th] -clock_fall [get_ports fp1_do[*]] -add_delay  FPGA2: set_input_delay -clock fp2_ci -max [expr $fp1_max_tco] [get_ports {fp2_di[*]}] -add_delay set_input_delay -clock fp2_ci -min [expr $fp1_min_tco] [get_ports {fp2_di[*]}] -add_delay set_input_delay -clock fp2_ci -max [expr $fp1_max_tco] -clock_fall [get_ports {fp2_di[*]}] -add_delay set_input_delay -clock fp2_ci -min [expr $fp1_min_tco] -clock_fall [get_ports {fp2_di[*]}] -add_delay  By TQ,the slack of setup timing is about 6ns to 7ns on both FPGA,but the slack of holdup timing is only about 0.5ns on both FPGA. For this case,Need I adjust the value of fp2_th to increase the slack of holdup timing?

[Altera_Forum]

No, that's good.  

The hold slacks are, generally, small.

[Altera_Forum]

The detail of the test mentioned above. 

FPGA1 : registers to Outputs(Setup) https://www.alteraforum.com/forum/attachment.php?attachmentid=6642  FPGA1 : registers to Outputs(Hold) https://www.alteraforum.com/forum/attachment.php?attachmentid=6643  FPGA2 : Inputs to registers(Setup) https://www.alteraforum.com/forum/attachment.php?attachmentid=6644  FPGA2 : Inputs to registers(Hold) https://www.alteraforum.com/forum/attachment.php?attachmentid=6645  post-sim with connecting the both FPGA in series https://www.alteraforum.com/forum/attachment.php?attachmentid=6647   the test's timing didn't reach the best effect. At this case,the slack of setup had 5ns to 7ns.Wasn't it enough? How to judge whether the timing has reached the best effect by the slack value?

[Altera_Forum]

What effect were you hoping for? 

As far as I can see, all the signals there have good setup/hold margins and you should not be getting any violations in post-fit simulation.

[Altera_Forum]

--- Quote Start ---  What effect were you hoping for? As far as I can see, all the signals there have good setup/hold margins and you should not be getting any violations in post-fit simulation.  --- Quote End ---    The timing was OK,But the clock dindn't capture the data at the middle position of the data. And I hope it does.Do you have any way to do that?

[Altera_Forum]

On FPGA2, have the PLL generate a clock with a 90º phase shift and use that to latch the data. 

You'll notice your setup slacks will decrease and your hold slacks will increase.  PS: Somehow I forgot but when using DDR, you should set I/O constrains for both edges of the clock. This is done by repeating the constraint with -clock_fall -add_delay set_input_delay -max XX -clock clk [get_ports fp1_co] set_input_delay -max XX -clock clk -clock_fall [get_ports fp1_co] -add_delay Same thing for min output delay and input delays.

[Altera_Forum]

--- Quote Start ---  On FPGA2, have the PLL generate a clock with a 90º phase shift and use that to latch the data. You'll notice your setup slacks will decrease and your hold slacks will increase.  PS: Somehow I forgot but when using DDR, you should set I/O constrains for both edges of the clock. This is done by repeating the constraint with -clock_fall -add_delay set_input_delay -max XX -clock clk [get_ports fp1_co] set_input_delay -max XX -clock clk -clock_fall [get_ports fp1_co] -add_delay Same thing for min output delay and input delays.  --- Quote End ---    I see.Thanks. And I encountered one case.However I adjusted the value of the tH,not all FPGAs could meet the timing.either FPGA1 or FPGA2 couldn't. Does it mean that the timing cann't be met only through the timing constraint,and the desigh is needed to modify?For example,using a PLL to shift the phase  of the output clock.Right?