How to equilibrate a Clock Tree with Muxes

[Altera_Forum]

I'm facing a problem in my design.:eek: 

I'm using Quartus 9.0.  In my design (coming from ASIC world), i've somes Flip Flops clocked onto a first clock CLK1.  I've somes Flip Flops clocked onto a second clock CLK2.  The CLK2 is in fact a MUXes between CLK1 and another clock, named CLK3.  CLK3 and CLK1 are unrelated, so no problem with them.  I've put a global buffer onto CLK1 and CLK2 (using assigment editor).  But how can i constraint in timequest to align all FFs onto CLK1 "clocktree" (especially those clocked with CLK2) ? I think i've to use -group but how ?:confused:  How can i do the same using classic timing analyser ?  Many Thanks.:) Regards.

[Altera_Forum]

--- Quote Start ---  I'm facing a problem in my design.:eek: I'm using Quartus 9.0.  In my design (coming from ASIC world), i've somes Flip Flops clocked onto a first clock CLK1.  I've somes Flip Flops clocked onto a second clock CLK2.  The CLK2 is in fact a MUXes between CLK1 and another clock, named CLK3.  CLK3 and CLK1 are unrelated, so no problem with them.  I've put a global buffer onto CLK1 and CLK2 (using assigment editor).  But how can i constraint in timequest to align all FFs onto CLK1 "clocktree" (especially those clocked with CLK2) ? I think i've to use -group but how ?:confused:  How can i do the same using classic timing analyser ?  Many Thanks.:) Regards.  --- Quote End ---     Hi,  I' pretty sure that you can not use the Classic Timing analyzer. You have to use Timequest. Have a look into the TimeQuest Cookbook:  http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf?gsa_pos=4&wt.oss_r=1&wt.oss=cookbook  Kind regards  GPK

[Altera_Forum]

Thanks for the link. 

 But it seems that my problem is not exactly detailled in this document, or i've missed it.  Could you explain me precisely how to do ? Thanks a lot.

[Altera_Forum]

--- Quote Start ---  Thanks for the link.  But it seems that my problem is not exactly detailled in this document, or i've missed it.  Could you explain me precisely how to do ? Thanks a lot.  --- Quote End ---    Hi,  maybe I missed somethig. Are CLK3 and CLK1 unreleated ? If, yes and you have paths between the registers in your different clock domains you could not set any constraints like setup or hold, because the phase of the clock edge is continuous changing. You have to design a real clock domain crossing.   I have a small project attached. Is that like your design ?  Kind regards  GPK

[Altera_Forum]

Hello, 

 Some teacher once upon a time said me that is not a good practice of design to use combinatorial nets in the clock inputs. It can cause some problems because the propagation delays.  Good luck.  Bye.

[Altera_Forum]

--- Quote Start ---  Hi,  maybe I missed somethig. Are CLK3 and CLK1 unreleated ? If, yes and you have paths between the registers in your different clock domains you could not set any constraints like setup or hold, because the phase of the clock edge is continuous changing. You have to design a real clock domain crossing.   I have a small project attached. Is that like your design ?  Kind regards  GPK  --- Quote End ---    In my design, CLK3 and CLK1 are unrelated.  Your example is close to mine.   So, how is it possible to align clock edge onto "inst1" and onto "inst/inst7" ? I saw that there is 2 globals. One onto CLK1 and one onto mux_a\out . But the delay of theses global buffers and the delay in the mux is not constrained. So, there is no reason that theses 2 clocks are in phase.  Another way to say it, is "how is it possible to constraint quartus fitter/router to have NO skew between the clock CLK1 that feds inst/inst7 and clock mux_a\out that fed "inst1"?  Regards.

[Altera_Forum]

--- Quote Start ---  Hello,  Some teacher once upon a time said me that is not a good practice of design to use combinatorial nets in the clock inputs. It can cause some problems because the propagation delays.  Good luck.  Bye.  --- Quote End ---     Your teacher is right and i'm full agree with him ;). Unfortunately, this design is a porting of a ASIC one,and i cannot (as much as possible) change anything in it. :mad:  It seems that in ASIC it is possible to align the 2 clocks by using specific constraints onto place/route tools.:rolleyes:  Regards.

[Altera_Forum]

--- Quote Start ---  Your teacher is right and i'm full agree with him ;). Unfortunately, this design is a porting of a ASIC one,and i cannot (as much as possible) change anything in it. :mad:  It seems that in ASIC it is possible to align the 2 clocks by using specific constraints onto place/route tools.:rolleyes:  Regards.  --- Quote End ---    Hi,jj st  yes, in the ASIC world it is much easier to align the clocks as you can do it in an FPGA.   In my point of view you have two problems. First, when you say that CLK1 and CLK3 are unreleated, then you have a so-called clock domain crossing in your design. The Problem is that the position of the clock edges will shift all the time. It is not possible to solve this with constraints. You have to take care for this in your design. If you say that the design comes from an ASIC I'm pretty sure that the design is (hopefully) designed in this way.   When the clocks are related you run into the problem of the so-called clock skew. The clock routing for both clocks will be different. That could cause time violation, e.g Hold time violation in case that the paths between source and destination registers are short. In case that we are talking only about a few signals and the clock skew is small Quartus should be able to solve the problem , when you use the option :  Settings -> Fitter settings -> Optimize Hold timing -> All paths  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,jj st  yes, in the ASIC world it is much easier to align the clocks as you can do it in an FPGA.   In my point of view you have two problems. First, when you say that CLK1 and CLK3 are unreleated, then you have a so-called clock domain crossing in your design. The Problem is that the position of the clock edges will shift all the time. It is not possible to solve this with constraints. You have to take care for this in your design. If you say that the design comes from an ASIC I'm pretty sure that the design is (hopefully) designed in this way.   When the clocks are related you run into the problem of the so-called clock skew. The clock routing for both clocks will be different. That could cause time violation, e.g Hold time violation in case that the paths between source and destination registers are short. In case that we are talking only about a few signals and the clock skew is small Quartus should be able to solve the problem , when you use the option :  Settings -> Fitter settings -> Optimize Hold timing -> All paths  Kind regards  GPK  --- Quote End ---     I'll try this. Thanks.