How to generate 128-bit DDR3 interface on Cyclone 10 GX

[DKron4]

I'm trying to implment a 128-bit DDR3 interface in a Cylone 10 GX 10CX105. I have made a design to test this, but cannot get successful placement. Is there a reference example of how to configure such an interface? According to "Intel Cyclone 10 GX EMIF IP Product Architecture" (UG-20116), DDR3 interfaces up to 144 bit are supported.

My ultimate goal is to get 4 DDR3 SODIMM modules connected to 1 FPGA for a total of 64GB of memory. The ping pong interface seems to allow an interface this wide, but I need 8 chip selects, and only 4 are allowed. With two 64-bit interfaces, I can't get successful placement. Is there any way to achieve this?

[DKron4]

Apologies, I realized I posted this to the wrong board. I reposted it to FPGA Intellectual Property, but I get an error while trying to delete this post.

[NurAida_A_Intel]

Hi DKron4, My apology for the delay in response. I'm afraid there is no other way as the error message in Quartus also stated clearly on the memory limitation. The maximum no of chip selects allowed is 4. I am sorry for the inconvenience caused. Regards, NAli1