How to generate a pulse smaller then cycle time

[Altera_Forum]

Hi Every body, i am a new user of FPGA and i am suffering from a basic problem, any one can help please :confused:  

i am using 16 MHz clock pulse of PCI for my FPGA, it corresponds to cycle time of 62.5 ns. Now i want to generate a pulse of cycle time smaller then this (62.5 ns). how can i do it? provided 16 MHz clock cannt be changed, and if it is changed then the pulse to be generated should be still less then the cycle time corresponding to that frequency. can i use another oscillaor for this pulse generation and this 16 MHz pulse for rest of my logic

[Altera_Forum]

Use one of your FPGA's PLLs to generate a higher frequency clock from the 16 MHz clock.

[Altera_Forum]

thx for your help dear. how small pulse width can i generate using a PLL

[Altera_Forum]

Like any FPGA design, how fast will it run will depend on your target FPGA, it's speed grade, your design and the I/O standard you'll be using. 

 As a ball park number, 10 ns (100 MHz) is generally possible.

[Altera_Forum]

thx for your guidence and elp sir.......... regards