To change external memory access time?

[Altera_Forum]

Hello, 

 I have a board with Nios using external SRAM built in two flavors: the one is fast 10ns SRAM the other is a battery-backed 70ns SRAM. The boards will have different software to work on each build.   My goal is to have both boards configured with the same FPGA file.   Is there a way to configure a tristate slave with 70ns access time and than change this access time to 10ns from the software somehow?   My code loads from flash memory to SRAM and executes from SRAM.   Any ideas?

[Altera_Forum]

The number of wait states for an SRAM are fixed when the SOPC builder project compiles. 

The only way around this that I can see is to write your own component in HDL for the SRAM, and use the wait_request signal to pause the master. Your HDL component could contain a register to configure the number of cycles to keep the wait_request signal enabled for each access.

[Altera_Forum]

Avalon Tristate Slave does not even have wait request signal. 

What kind of HDL component do you have on your mind? How deep in the Avalon switch fabrics would I have to do into?

[Altera_Forum]

You could do a traditionnal Avalon slave that connects to your SRAM through a conduit, instead of using the tristate interface. I did it for a ZBT SSRAM and it is quite easy to do. 

Of course this would only work if you don't share the SRAM pins with another component.

[Altera_Forum]

I do share the SRAM pins with the CFI chip.