How to get C program or openCL program to call or interact with a preconfigured FPGA

[Altera_Forum]

Hi, 

I am new to FPGA's but I am wondering is it possible to to have a preconfigured FPGA already pre-built to do a particular task and have a C or C++ or openCL function call the FPGA and send and receive data to and from it. How would a scenario like this be done?? Appreciate any response. Thanks for your time.

[Altera_Forum]

I'd say this is one of the main purposes of FPGAs. 

But what do you need exactly?  You said 'call' the FPGA. So I guess you have an external microprocessor or any other CPU and you want to offload some intensive elaboration to FPGA. Is this correct?

[Altera_Forum]

--- Quote Start ---  I'd say this is one of the main purposes of FPGAs. But what do you need exactly?  You said 'call' the FPGA. So I guess you have an external microprocessor or any other CPU and you want to offload some intensive elaboration to FPGA. Is this correct?  --- Quote End ---    Hi Cris72,  Yes that is correct, for example lets say I have a c program that adds tow vectors together that I implement using the cpu, but lets say I also have a FPGA built to specifically multiply two large matrices together. I want to be able to have a C function that can specifically call on the FPGA to do this calculation, pass it the necessary data, receive the result. Its the I/O interaction/communication between the C program function and FPGA that I am unsure about.  In openCL you compile the kernel code and then it gets synthesized and built on the FPGA. With that all the memory mappings and I/O configurations get done for you behind the scenes. But what about if you already have a pre-built FPGA that you wrote yourself with verilog and now you want to be able to write your c function that can call on it to do a task. I hope this makes sense, sorry if it sounds convoluted, I am new to this and don't fully grasp the full picture yet.  thanks for taking the time.

[Altera_Forum]

First of all, for the specific example you give it's quite likely that you can do matrix multiplies faster with a multi-core CPU with vector instructions or in a GPU than an FPGA could do them. 

 One way is to have dedicated memory attached to the FPGA. The FPGA is addressable by the CPU and the software arranges for the incoming data to be placed in the FPGA dedicated memory. Once the data are in FPGA memory, the CPU writes to registers in the FPGA telling it what to do. When the FPGA finishes it can interrupt the CPU, or the CPU can periodically check registers in the FPGA to see if it is done.

[Altera_Forum]

--- Quote Start ---  First of all, for the specific example you give it's quite likely that you can do matrix multiplies faster with a multi-core CPU with vector instructions or in a GPU than an FPGA could do them.  One way is to have dedicated memory attached to the FPGA. The FPGA is addressable by the CPU and the software arranges for the incoming data to be placed in the FPGA dedicated memory. Once the data are in FPGA memory, the CPU writes to registers in the FPGA telling it what to do. When the FPGA finishes it can interrupt the CPU, or the CPU can periodically check registers in the FPGA to see if it is done.  --- Quote End ---    Hi Galfonz, Thanks for your reply. I wonder is it possible to have OpenCL do this for me already. As in when you synthesise an OpenCL kernel all this is already done. But if I build my own implementation using verilog can I still use openCL to implement the FPGA. Also If I want to add in extra hardware to my FPGA board could I use openCL to communicate with this without too much hassle? Thanks

[Altera_Forum]

That depends. Is your goal to crunch numbers or learn how to work with FPGAs using number crunching as an example. If you goal is number crunching you will find it much easier to use a GPU. Even if the processing ends up quicker on an FPGA you will be ahead because GPUs are cheaper than FPGAs and faster to develop for. You would use an FPGA if you need to do massive I/O and crunch numbers. 

 I've not used openCL, but I expect it is easier to use than Verilog/VHDL with the trade off of lower performance and greater FPGA resource usage for any given task.