How to give phase shift to dqs signal.

[Altera_Forum]

Hi, 

I am working on NAND flash controller IP. The nand flash gives edge align data with DDR during read operation. I have used altera bidirectional ddio. I want to make this edge align data to center align. For that i need to give timing constraint to dqs pin. The fpga pin connects with dqs is not the dedicated clock pin and hence i can't use PLL to generate phase shift. I also have the board on which dqs pin matched with dedicated dqs pin of fpga. So how can i apply constraint to this pin? I tried with I/O delay but it didn't work so far. I have attached the file for with picture to let you know what exactly I want to do. Further the frequency of dqs is 20Mhz, 33Mhz, 50Mhz, 67Mhz and 83Mhz for mode 0,1,2,3 and 4 respectively. Please help me solved out this issue.   Thanks in advance   Regards,   Krupesh

[Altera_Forum]

A simple solution is possible if you have a spare PLL: create a higher frequency clock and use it to sample dqs and generate a shifted version.

[Altera_Forum]

I agree with cris72. I tried putting constraints and they seem weird than whats on xilinx. 

 However using High frequency clock would help.  Just keep in mind if you plan to flop DQS on clcok(high speed) and give it to DDIO, it may not like it. You might have to pass it through some global glock net.

[Altera_Forum]

Thanks for your reply. 

 So you mean to say that I have to sample dqs clock at higher frequency and make it centre aligned right? By trial and error method I have to do this or there is any equation like I can use 2x or 3x clock then dqs.One more thing Nand Flash Device supports different operation modes in which dqs frequency is different for eatch mode.   Regards,   Kruepsh

[Altera_Forum]

If you always need it to be center aligned, a 2x clock should be enough.

[Altera_Forum]

Hi, 

  During read operation Nand Flash Device generates dqs clock.So phase difference between dqs clock and 2x clock which is generated using pll may be diffrent right?Still I can use 2x clock to get centre aligned data?   Thanking you,   Regards,   Krupesh

[Altera_Forum]

With PLL you must use a predefined input frequency, so you can't use a clock which changes depending from mode, unless you want to reconfigure PLL at runtime. 

You could generate a fixed clock at the maximum 2x frequency, say 166MHz, then sample dqs at this rate with some logic like this: mode 4 (83MHz): toggle dqs out pin one clock after dqs in edge mode 3 (66MHz): toggle pin one or two clocks after dqs in edge mode 2 (50MHz): toggle pin two clocks after dqs in edge mode 1 (33MHz): toggle pin 3 clocks after dqs in edge mode 0 (20MHz): toggle pin 4 clocks after dqs in edge You will not have an exact 180 degree phase, but I think it would be enough for your purposes. I presume the exactly center aligned constraint is critical only at the 83MHz mode, isn't it?  Cris

[Altera_Forum]

HI Krupesh, 

 I have done similar experiment and it works!  What I did, instead of using DQS for data sampling (the dqs freq 50Mhz) , used 50Mhz internal clock.I have 50Mhz internal clock driving DDR.  On read instead of sampling data on the DQS we sample it on internal 50 Mhz clcok with a controlled phase shift. The phase can be produces in multiples of 45 deg using 200Mhz clock using both the clock edges and putting a clock mux.  This mux can even be selected and controlled using a register to align the latching clcok and data so that you wouldnt miss it.  You can try this or even a 2x clock(in my case it could be 100Mhz) be used to create phase shift of the order of 90 degs.

[Altera_Forum]

Thank you very much Cris and alteraguy1. 

 I have implemented the logic which Cris has suggested. It works for almost all the modes.I think what alteraguy1 has suggested is also correct. I will try that also.  Again I really appreciate your reply.  Regards,  Krupesh.