I’m planning to design a signal processing system with Arria 10 SOC, using ALTERA_FP_FUNCTIONS, on-chip RAM and FFT IP Core. Each of IP Core works correctly with the frequency up to 350MHz, but the maximum frequency drop to 250MHz after integrating them in a single project. No extra combinational logic in the design.Checking the netlist viewer, there’s only one buffer on the path of PLL’s output, which is the main clock and all IP Cores trigger on the rising edge of main clock. I set the main clock as a auto global clock in the Assignment Editor, but the result of timimg analysis doesn’t improve. Is there any way to solve this problem? Can I solve this problem by adding clock buffer on the path of main clock? If the answer is positive, how to add clock buffer? THANKS. Regards.
Did you do a timing analysis? Use report timing (setup, hold) to the main clock in Timequest. You will get a list of the top failing paths.Are all outputs of the IPs registered? You may need to adjust the timing constraint file (toplevel, pinning changed). Jens