Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20733 Discussions

How to ignore Latches for Timing analysis

Altera_Forum
Honored Contributor II
‎12-06-2016 10:48 PM
1,043 Views

Hi , 

 

I have latches (as combinational loops) which must be used in my design. These latches acts as start/end point for timing analysis.  

So my design is not getting properly optimized. 

 

Is there any way, i can ignore these latches from timing analysis & for synthesis/Fitter optimizations. 

I have tried False path/ disable timing constraints and it didn't work. Also tried switch -no_latch for timing but its not useful. 

 

Regards, 

NKD
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎12-10-2016 09:25 PM
294 Views

Hello , 

 

Can I guide tool to ignore latches as sequential elements. Either in synthesis or Fitter stage. 

 

Regards, 

NKD
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.