How to implement Content Addressable Memory in Stratix V FPGA

[Altera_Forum]

Hi,  

 I will be working on a Stratix V development platform in a couple of days, and I m curious to know whether Content Addressable Memory can be modelled in it. I ve checked with the UserManual of Stratix V and could not find Embedded System Block in Stratix V. Instead Embedded Memory containing M20K and MLAB is present. So my question is it still possible to use AltCam Megafunction with Stratix V FPGA? Will it be functioning same as described in "AN119-Implementing High Speed Search Applications with Altera CAM" document?     Thanks in advance, Jeebu Jacob Thomas

[Altera_Forum]

The modern FPGAs don't have CAM any more. You can emulate a CAM using a regular memory block, but of course it uses a lot more memory bits. You can have a look at pages 9.6 and over in the advanced synthesis cookbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/stx_cookbook.pdf) for a way to implement it.

[Altera_Forum]

--- Quote Start ---  The modern FPGAs don't have CAM any more. You can emulate a CAM using a regular memory block, but of course it uses a lot more memory bits. You can have a look at pages 9.6 and over in the advanced synthesis cookbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/stx_cookbook.pdf) for a way to implement it.  --- Quote End ---    From the devices mentioned in the OPs document, CAMs havent been in FPGAs for 10+ years