How to implement LDPC over GF(2^m) in System verilog?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

How to implement LDPC over GF(2^m) in System verilog?

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Hai friends..

I was assigned a work to implement parallel LDPC GF(2^m) decoder using system verilog in Altera DE2 board.

I dont know where to start.

Can anyone please suggest an idea for me from where to start this work?

Also can anyone please suggest study material regarding this work?

I have to complete it within this month.

I will be thankful to any suggestion from this forum.

Awaiting your reply....

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