Multiple READ and WRITE controllers to SDRAM with AVALON BUS (No Nios)

[Altera_Forum]

Hi, 

 Working on the following project :    - Read 1 images from 2 camera's (2 image's) -> store to SDRAM  - Make calculation on each image -> store to SDRAM - Read out calulations from SDRAM -> Send out to external µC - ... - ... Will do other stuff with it, in the future   Each time i need to store something i use a master TEMPLATE from SOPC who make's the translation for the AVALON bus.    From the AVALON bus to the SDRAM I use the SDRAM Controller.   So on the AVALON bus I now have  6 Components who Write (master Template) 2 Components who Read (master Template) and 1 SDRAM controller   Outside the SOPC i made a controller who is managing the components (READ and WRITE) there usage of the Avalon Bus. (It works for most of the time)   When data traffic increases it fails and i get BUFFER_FULL of the WRITE controllers.      Is there a other way to handle multiple write's to one SDRAM ?    Holding in mind:   - Camera's generate the image at the same time. - Result of calculations is given at the same time.  - More calculations will follow - Never worked with Nios before   Thx for possible answers.

[Altera_Forum]

I assume you are using these: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html?gsa_pos=1&wt.oss_r=1&wt.oss=template 

 The write buffer in that template will become full if data continues to enter into it while the write master is waiting. It could be waiting because your controller hasn't told it to move any data or the arbiter for the memory hasn't let it continue (something else is accessing the memory).  You might want to use a DMA for what you are doing. The data from the camera could be formed into Avalon-ST using a bridging component and then the DMA could take the streaming data and pipe it into memory. Likewise the same could happen in reverse for sending data back to the outside.

[Altera_Forum]

Does the DMA involves the usage of a CPU ?

[Altera_Forum]

A DMA is told what to do by a CPU normally but the CPU stays out of the data path. For example the CPU in your case would tell the DMA to read 'x' number of bytes from your camera and write them to address 'y' in memory. 

 Your external micro-controller could be the one in control of the DMA. If you think the CPU telling the DMA what to do will add too much overhead then you may be able to use a scatter gather DMA which will buffer multiple descriptors (transfer requests) to hide any CPU to DMA inefficiencies.