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How to implement LFPS in Cyclone 10 GX transceiver IP

Yt_aem
Novice
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Hi,

I am gonna design a USB3.0 port by using the Cyclone 10GX transceiver IP. In USB3.0/3.1 it needs to send a side band signal, Low frequency Period Signal(LFPS) to other partners . Is there anyone knowing how to combine it into the transceiver?

 

Very appreciated! 

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ZiYing_Intel
Employee
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Hi,


Thanks for submitting the issue. Allow me have some time to look into the issue and I will get back to you with findings.


Best regards,

zying


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ZiYing_Intel
Employee
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Hi Yt_aem,


"In USB3.0/3.1 it needs to send a side band signal, Low frequency Period Signal(LFPS) to other partners." Can you clarify more about this? May I know that it will send to which things?


Best regards,

zying


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Yt_aem
Novice
2,816 Views

Hi Zying,

In USB3.0/3.1 protocol, when you plug in a USB C connector the first thing of first is that both source and device ends send out a low frequency clock signal about 10 MHz over the transmit line of the USB to let the partner know "I am connected" or to wake up each other then they go to training mode. See USB3.0/3.1 spec.

From your Intel Dev board for cyclone 10 GX there is a reference design for USB3.1 interface in circuitry. See sheet 24 of the schematic attached. I did not find any circuit to support this side band clock signal. That looks like it has to be generated from the cyclone 10 GX transceiver itself. If this is true, my question is, how to configure the transceiver by Quartus Prime software?

Thanks

Yaoting

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ZiYing_Intel
Employee
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Hi Yt_aem,

 

I don't found any information that related to LFPS for transceiver itself but maybe you can try to modify the logic inside it.

 

Best regards,

zying


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Yt_aem
Novice
2,764 Views

How to change the logic inside the transceiver? do you mean at fabric side?

Transceiver includes PMA and PCS layers. We need 8b/10b encoder and decoder of PCS. The LFPS must happen at PMA layer. After PCS in transmitting channel we can't send out a 01010101... sequence signals to PMA. So, at fabric /logic side, it is impossible to design the LFPS signal to my understanding.

Since in your dev. kit board there is a USB3.1 circuit having been designed already, I bet, you guys should give out such kind of design guideline, don't you?

Looking forward to your helps. I am stuck there.

Appreciate a lot!

 

yaoting 

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ZiYing_Intel
Employee
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Hi Yt_aem,

 

I found the Cyclone 10 gx schematic. Hopefully it is useful to you. Besides that, you also can go to the link below  https://www.rocketboards.org/foswiki/Main/WebHome  which got a lot project that you can refer to.

 

Best regards,

zying

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Yt_aem
Novice
2,570 Views

Hi ZiYing,

I have not found any USB3 related tech info directly from the link you provided. 

Still, you have not solved the issue! 

Is there any way to have me get through the problem?

 

Yaoting

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ZiYing_Intel
Employee
2,594 Views

Hi Yt_aem,


Since no hear any feedback from you, I am now close the case. If you have any issue after the case close, please do feel free to submit another issue. There will have people reach out to you.


Best regards,

zying


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ZiYing_Intel
Employee
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Hi Yt_aem,

 

For the realization of the USB3 using Intel Cyclone 10 GX FPGA, you may refer to link below Realization of USB3.1 Gen2 (10Gbps) using Intel® FPGA - Semiconductor Business -Macnica,Inc.

For further information about the USB3.1, you may refer link below https://www.intel.com/content/www/us/en/docs/programmable/683696/current/usb3-1-type-c-interface.html

 

Best regards,

zying


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Yt_aem
Novice
2,428 Views

Hi ZiYing_Intel,

The first link is to tell us general info about the use of Cyclone 10 GX FPGA to form a USB3.1 link but without any info of how to do it, no mention to LFPS.

The second link is just an introduction of the Dev. kit of Intel, which is exactly I gave you in above talks with you.

My issue is a design one, not an overview info can solve it. Since I have your dev kit, I do need your board designer or FPGA designer to teach me how to complete the USB3.1 design over the board. Can you help through?

Thanks

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Farabi
Employee
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Hello, 

 

Please refer to attached C10GX220 devkit sch and go to page 24. 

In page 24, you will see component TUSB1002RGER, which is the one handling the LFPS. 

datasheet link: https://www.ti.com/lit/ds/symlink/tusb1002.pdf (see page 14)

 

Regarding USB3.1 IP for this board is provided by SLScorp and this is paid IP. If you need access to the IP and its internal design, you may need to contact SLSCorp. link: https://core.slscorp.com/ip-cores/communication/eusb-3-1-gen-2-device-controller-eusb31sf.html

 

regards,
Farabi

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Yt_aem
Novice
2,358 Views
Hi Farabi,
Thank you for your response.
But, from the block diagram of TUSB1002 (@page14) it only shows that it only can detect LFPS at RX ports while doesn’t mention how to generate LFPS at TX ports.
Please advise further. Very appreciated!
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FvM
Honored Contributor I
2,341 Views
Hi,
according to my knowledge, Agilex 7 F-Tile PHY implements the first and only LFPS detector available with Intel FPGA. Apparently no dedicated LFPS generator. Presume it has to be implemented by oversampling, should work for Cyclone 10 GX too.
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ZiYing_Intel
Employee
2,262 Views

Hi Yt_aem,

 

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

 

Best regards,

zying


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