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Quartus thinks reset signal is a clock signal

sth125
New Contributor I
1,648 Views

Hello, 

My device is a 5M1270ZT144C4 and I am using Quartus Prime Version 22.1std 2 Build 922 07/20/2023 SC Lite Edition.

 

I am having a similar issue as the post https://community.intel.com/t5/Intel-Quartus-Prime-Software/Diagnosing-quot-signal-was-determined-to-be-a-clock-quot-message/m-p/22206#M4702.

 

The Timing Analysis shows the Reset signal as a clock signal. 

 

None of the pins are defined and all of the logic is defined on diagrams (i.e. no VHDL/Verilog code).   The reset signal does not go to the clock inputs of any logic.  The image below shows the Clock signal (CLK1) and the Reset Signal (CPURST_25).

 

What can I do to fix this issue.


Stephen

 

 

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_AK6DN_
Valued Contributor II
1,624 Views

The one image you provide is completely insufficient to provide solution(s) to your problem.

You need to provide either the code or schematic connections of the RESET line to understand why you think Quartus thinks it is a clock.

The RESET line will appear in the timing analysis, as there is a timing associated with the RESET to DATAOUT arc in a cell.

That does not mean Quartus thinks RESET is a clock, only that their is a timing dependency on DATAOUT from RESET.

So long story short you need to provide a lot more documentation on your design.

sth125
New Contributor I
1,601 Views

This code is for the company I work for, so I won't be able to supply you will all the logic diagrams.

I think I might have fixed it by right clicking on the signal in the the timing analyzers clocks window and selecting "remove clock".  That will remove it from the sdc constraints file.

Do you think that is the fix or is it just covering up the issue.

 

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sstrell
Honored Contributor III
1,595 Views

As mentioned, without more detail on the design or seeing the .sdc file, there's no way to tell if this is a valid fix.

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Nurina
Employee
1,575 Views

Hello,


I need more details and information to investigate your problem.

Is it possible for you to share the .qar file of your project through email?

I'm dropping you an email so you can send me your design through there.

To generate a .qar file, go to Project>Archive Project.


Regards,

Nurina


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Nurina
Employee
1,541 Views

Hi,


Can you provide some update?

I have dropped you an email so that you can share your design there, please search for email subject "Intel Customer Support - Case #: 06034432"


Regards,

Nurina


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Nurina
Employee
1,482 Views

Hi,


We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

 

If any answer from the community or Intel Support are helpful, feel free to rank your support experience by rating 4/5 survey. Please let me know of any inconvenience so that I may improve your future service experience.

 

Have a great day!


Best regards,

Nurina


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sth125
New Contributor I
1,356 Views

Hello Nurina,

I can't post the design.

I would be best if you could point me to some documentation on this subject.

 

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