How to implement high speed port(such as HDMI) into FPGA chips

[Colin_liu]

Hi experts, We just do some low speed IO function previously and some high speed port needed to be implement recently. Could you please help some confusion.

Take HDMI port as example:

1.We can find intel chip IO standard clearly as showed in Quartus. At the same time, HDMI formal SPEC/protocols defines differential ports electricals. We can not match HDMI SPEC with Quartus I/O standards well. Quartus shows IO standards such as LVDS/3.0V PCI/differential HSCL, etc. It seems no TMDS standard(HDMI) can be found. Does it means we can not implement HDMI bus on such chips. (Meanswhile we search some FPGA chips but can not find HDMI TMDS bus IO standard directly). Could you teach us how to match high speed electrical standard to intel FPGA IO standard? Does it have any details electrical  SPEC documents for intel FPGA chips.That we can confirm intel chip IO standards with high speed bus protocol SPEC.

2.How to determine/fine tune Differential Voltage swing+/- in Quartus? Or can we adjust Differential Voltage swing+/- in Quartus? such as +-200mv or +-400mv.

3.Does this website has any hardware schematics reference design for FPGA chips.

Thanks very much.

[FvM]

Search Intel web site for HDMI and you are linked to HDMI IP user guide, HDMI PHY user guide and AN837 describing implementations on recent FPGA with Gigabit interface like Cyclone 10 GX and Arria 10. There also links to hardware schematics in AN837.

As you already found out, IO standard of Gigabit transceivers isn't compatible to TMDS. Intel suggests AC coupling for a direct connection. https://www.intel.com/content/www/us/en/support/programmable/articles/000074904.html
The available evaluation boards are however using a dedicated TMDS driver chip between FPGA and HDMI sink. I'm no HDMI expert, but it's said that DC coupling is required during link initialization.

[Colin_liu]

Thanks sir,

You give us valuable informations. It seems we have to consider more aspect when it comes to high speed port design. We are trying to understand your information well.

[ZH_Intel]

Hi Colin liu,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi Colin liu,

Apologize for the delayed response as we encounter some technical difficulty.

Thank you FvM for sharing the information.

Below is the link to the information shared by FvM for your reference:

1. HDMI Intel® FPGA IP Core Landing Page 
2. HDMI Intel® FPGA IP User Guide
3. HDMI PHY Intel FPGA IP User Guide
4. AN 837: Design Guidelines for HDMI Intel FPGA IP

Is there anything else I can help you with regards to this case?

Do you still have further inquiries on this case?

If no further inquiries, I will transition this thread to community support.

Thank you.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi Colin liu,

Since your question has been addressed and there is no further inquiries, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you.

Best Regards,

ZulsyafiqH_Intel