How to implement this logic in one Marocell?

[Altera_Forum]

Hello: 

 The macrocell has 1 register.   How many product terms of 1 macrocell? 16? And a ring lcells can be implemented inside 1 macrocell?   Can 1 register plus 1 lcell be implemented inside 1 macrocell? if can, and how to do that?   I did like attached file, and need 2 marcocells.

[Altera_Forum]

My object is to get more gate delay time. In fact, i did like this figure and the tool will synthesize away the or gates, not gate..... How to let the QII reserve these gates?!

[Altera_Forum]

My mean is what is the most longest time ,which the input can be delayed inside one macrocell?

[Altera_Forum]

The above logic circuit is inadequate in several respects: 

- a LCELL implements logic operations by a LUT. The delay doesn't depend on the inplemented logic function. So it's meaningless to chain multiple logic symbols. - in combinational mode, the register is bypassed  There have been various post dedicated to the topic of logic cell delay, e.g. http://www.alteraforum.com/forum/showthread.php?t=3068  The design compiler is required to remove all redundant logic cells in regular operation, so synthesis attributes must be used to tell him that you want to keep certain logic cells. The delay achievable by logic elements depends on involved device family, process parameters, temperature. With Cyclone III, I found a typical delay of 0.2 to 0.25 ns.  P.S.: I assume, that you refer to FPGA or FPGA-like MAX II. CPLDs are handled by a different synthesis tool, that apparently doesn't support the "keep" synthesis attribute.

[Altera_Forum]

I am just using the MAX7000 devices. To archive some functions, I need to delay every signal 100ns to 3000ns. There are not enough resources for me to using buffer or counter to implement it. So I try to find a way of using combinational logics to implement the delay function. I want to implement more and more logic into single macrocell to get more and more delay time for each signal, and save more and more resource. 

  You konw, there are 32 trigger signals. The Min delay time is 100ns, and Max delay time is about 3300ns. I found epm7512 doesn't have enough resource to do that. Maybe I need to replace the chip to FPGA?!

[Altera_Forum]

It's not possible. The longest logic cell delay times can be achieved with CPLD by routing a signal to a spare I/O pin and reading it back through the input buffer. You know about the achievable delay range. External RC or LC delay circuits are another option if synchronous counters or shift registers can't be used.

[Altera_Forum]

The HW board has been finished. And the CPLD's input and output just are 32 input signals and 32 ouput pins, even no clock input.:mad: