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Altera_Forum
Honored Contributor I
1,225 Views

How to indicate a clk signal is differential in a MAX 10 FPGA

Hello,  

 

I am programming a MAX 10 FPGA and I would like to know how I can tell the device that the clk_in signal I defined in the top module is a differential clock. When compiling the project only one clock node is created (there's no way to know in advance that the signal is differencial, that's obvious) and I wonder if locating it to the CLK_p pin and then physically connecting the negative signal to the CLK_n would work or if I have to use some buffer or something else. 

Actually I tried to use a GPIO Lite IP module defining an additional signal in the top module and assigning both as positive and negative. That made the pin planner treat my clk_in signal as differential but on the other hand, the additional signal I created was unasigned and treated as a single signal so in the end it did not work. Any better idea? 

 

Thanks in advance!
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3 Replies
Altera_Forum
Honored Contributor I
97 Views

Did you set the clock input to a differential I/O standard in the Pin Planner? That should automatically enable a _n pin. Is the clock differential in your design's top-level port list?

Altera_Forum
Honored Contributor I
97 Views

I set it to a CLK_p pin that has an associated CLK_n pin but that did not generate any differential pair. I just tried what you suggested (I set my clk_in signal to a DIFF_p pin) and I got an error: 

 

Error (176554): Can't place PLL "LVDS:I_LVDS|LVDS_0002:lvds_inst|lvds_rx_pll" -- I/O pin clk_in (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device 

 

The clock is not differential in my top-level list and how to define it as differential was actually one of my questions because that might solve the problem. As I said I defined an additional input to use both as differential inputs for a GOPIO Lite IP module and it did not work 100% (a differential pair was automatically generated but the additional input I defined was unasigned so I had an extra signal that I did not really need).
Altera_Forum
Honored Contributor I
97 Views

I found a solution which was editing the .qsf file instead of using the Pin Planner so I manually told the tool the assignments I need. Thanks for your help anyways!

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