How to integrate two projects into one?

[Altera_Forum]

Hi, everyone. 

 A question about Quartus II 13.0 project design. I have finished designing two separate projects which are contained in different folders and now I want to combine them into one. What I have done is to create a new project in a new folder and copy the two project folders as subfolders of the new folder. After that, I have set the project libraries to contain the two subfolders in relative path.  Now the problem happens when I try to compile it. Such as showing these errors,  Error (12006): Node instance "myXG_DEV_top" instantiates undefined entity "XG_DEV_top" Error (12006): Node instance "pll_156_25_inst" instantiates undefined entity "pll_156_25_0002" Error (12006): Node instance "xaui_ip_core_inst" instantiates undefined entity "altera_xcvr_xaui"  I suppose once I set the path of a folder to the library, the compiler automatically finds the same name of the file from the folder that needs and refer to it. But it seems not working in mine. Did I do it in a wrong way, or should I set something else in addition?  Many thanks for any answer.

[Altera_Forum]

Quartus can no longer see the code for the three entities it lists: "XG_DEV_top", "pll_156_25_0002" & "altera_xcvr_xaui". 

 Within Quartus, under Project -> Add/Remove Files in Project. Point to the files that contain these design elements and add them to your new project.

[Altera_Forum]

Hi, 

One question I'd have here is what is the structure of your new, combined design?   When I've taken an existing project (with .vhd files containing the design logic) and added other design elements that are to exist at the same level in the design's hierarchy, I've needed to create a new top level unit. You can do this in Quartus, but I decided to do it manually by editing a new .vhd file with the top level E/A and having the other design units (top levels in their own, respective projects) as components in the new design. I then added the elements into the project (menu Project->Add/Remove Files in Project...)  I was then able to quickly locate and resolve any naming or mismatch issues during analysis & elaboration of the new, combined design. In simulation, I then refer to the combined top-level object in the tree view as the root for conducting the simulations. (In my case, I had created a separate project with VHDL TestBench logic that got merged into a project which was the Model under test, and which was the model going out to a Cyc III device).  In my experience, the trick is in adding the new design units to the project, making sure pinout between the projects maps correctly through the top-level unit, and making sure the use of scope prevents any name clashes. But having a new top level under which all the elements exist that you want to merge should alleviate a lot of problems. This experience wouldn't be radically different for Verilog than for VHDL, only that VHDL is more "finicky" about the connectivity.  It is also easy to check the structural correctness of the combined design using the schematic viewer (menu Tools -> Netlist Viewer -> RTL), to see that you have assembled what you want.  This is just another data point for you to consider. Hope this helps. cheers, jim

[Altera_Forum]

Hello guys..  

 I have to do with something like that: I have two projects, one of which is the main one. Now I want to include the second project into the first. So it could happen that some files of the second project have the same names of the files of the first project. In such a case I should rename all the overlapping files. There is a better way on achieving the same result ??  Thank you !

[Altera_Forum]

Maybe it could be clearer.. 

 Say I have a design.bdf with 4 input pins and two output pins. Then I want to create a vhdl file with the needed library.   In my_design.bdf I use some altera's components (eg lpm_mult, lpm_compare, etc etc) so my_design.bdf needs lpm_mult.qip, lpm_coompare.qip and so on. After that I create a hdl version of my_design.bdf and then have some simulations with modelsim.  Now I would be able to import my_design.vhdl in another quartus project. I think that I have to import my_design.vhdl but also the needed *.qip.    There is a synthetic way to accomplish this?

[Altera_Forum]

This is what I have understood.. 

 In quartus it's possible to create a hyerarchical project. So that there is a top level project in which you can import several subprojects. To do this you need first to create a subproject, then you must export it as a design partition (project->export design partition, it will create a .qxp file) and create also the symbol file (file->create/update->create symbol files).  Now open the top project and add the symbol file just created to your project's files. Start the synthesys and quartus will tell you that there is an undefined instance (which is the symbol just inserted).  Now click on: Assignement ->Design partition window -> new. Add the instance of the symbol of the subproject. Now click on: Project->import design partition->select the subproj partition and add its .qxp  Now you need only to compile the project.  By the way importing multiple subprojects could give some problems. As a standard the design partitions netlists are set as post-fit. So it could be possible that when you try to compile the subprojects will try to use the same logic areas. So you need to set the netlist type as post-synthesis.  In alternative one could use the logilock function and assign a specific area of the chip at each subproject.   By the way I have some questions:  1- How one can design correctly the logilock region for a subproject ?  I mean, I can create and compile my subproject and assign it a logiclock region that is the region that the fitter gives to it. Then I could do the same for another subproject. But when i put the two subprojects in the top project how can I ensure that the the two logilock regions will not overlap ? The best method probably is to assign the logiclock regions from the top project but you have to know the correct size and probably the needed block of the subproject.. it seems particularly tricky..  2- You can set the design partiotion netlist type also as 'source'. By the way it seems not working.. what am I missing ?  I'm still a little confused.. any suggestion is really appreciated !  Thank you.