How to let FPGA get access to HPS pins

[Altera_Forum]

I've got an Arrow SOCkit and it has a USB-UART connected to the HPS' pins, but I'd like to access the UART from the FPGA logic. Is this possible? If so how is it done? 

 Thank you!

[Altera_Forum]

You should be able to loan the HPS pins to the FPGA. 

 Go to the Hard Processor Configuration page in your Qsys module. In the 'Peripheral Pin Multiplexing' tab, there is a Peripherals Mux Table at the bottom. There you can select HPS pins to act either as a GPIO or be loaned to the FPGA. Click on the LoanIO buttons of the UART pins. Don't forget to disable the corresponding UART controller, or else it will complain about conflicts. Click 'Finish'.  Back in the Qsys project, the HPS entry should now have a new 'h2f_loan_io' conduit. Double-click to export the signals. Re-generate the system. If you look at the HDL example, you'll notice a few new signals. For example, if I loaned IO20:  .hps_io_hps_io_gpio_inst_LOANIO20 <-- Connect to top level inout pin .loan_io_in <-- Connect to FPGA logic .loan_io_out <-- Connect to FPGA logic .loan_io_oe <-- Connect to FPGA logic  All of the "loan_io_x" signals are the size of the maximum IO pins. For example, the Cyclone V these are [66:0].  The loan_io_oe controls whether the pin is an output. If '1' at the specified location (in this case loan_io_oe[20] = 1'b1), then it is an output, and you can control the pin writing to loan_io_out[20].  To read an input to the FPGA, just read loan_io_in[20], and set loan_io_oe[20] to 0.  Hope this helps.

[Altera_Forum]

--- Quote Start ---  You should be able to loan the HPS pins to the FPGA.  Go to the Hard Processor Configuration page in your Qsys module. In the 'Peripheral Pin Multiplexing' tab, there is a Peripherals Mux Table at the bottom. There you can select HPS pins to act either as a GPIO or be loaned to the FPGA. Click on the LoanIO buttons of the UART pins. Don't forget to disable the corresponding UART controller, or else it will complain about conflicts. Click 'Finish'.  Back in the Qsys project, the HPS entry should now have a new 'h2f_loan_io' conduit. Double-click to export the signals. Re-generate the system. If you look at the HDL example, you'll notice a few new signals. For example, if I loaned IO20:  .hps_io_hps_io_gpio_inst_LOANIO20 <-- Connect to top level inout pin .loan_io_in <-- Connect to FPGA logic .loan_io_out <-- Connect to FPGA logic .loan_io_oe <-- Connect to FPGA logic  All of the "loan_io_x" signals are the size of the maximum IO pins. For example, the Cyclone V these are [66:0].  The loan_io_oe controls whether the pin is an output. If '1' at the specified location (in this case loan_io_oe[20] = 1'b1), then it is an output, and you can control the pin writing to loan_io_out[20].  To read an input to the FPGA, just read loan_io_in[20], and set loan_io_oe[20] to 0.  Hope this helps.  --- Quote End ---    Thanks for your reply. This is very helpful, but I still have a couple of questions if you don't mind.  I've made the Qsys system which only has the HPS module and I've exported all HPS ports. This way I can instantiate the HPS in my VHDL code and connect all I/O's, clock and reset myself. I've then succesfully built the whole design, but my question is now, how do I program the HPS such that it gets configured with the Qsys configuration that I made?  I can see that there is a "handoff" folder which should contain the files needed to make a new BSP. I made the BSP and got a preloader bin file, but I'm not sure what to do from here?! Can I program the HPS directly or do I need to program either the QSPI or put the BIN on a SD card and use bootsel to select either one?   If I need to e.g. program the QSPI and use bootsel to select that the HPS needs to boot from QSPI, do I then need to have enabled QSPI inside the HPS in Qsys and mapped the I/O pins ?? And how do I actually program the QSPI? Is there a tool like the Quartus Programmer or some CLI command?  Thanks :-)

[VROGE2]

Hi,

I know this post is several years old but I am trying to follow it to use LoanIO to communicate with the UART on my DE10-nano SoC.

I have been trying to use the handoff folder to make a new BSP but I am having trouble doing so. Could you go into more detail on how you did that and if NIOS II Eclipse will work for this.

Van

[Altera_Forum]

You would need to boot from either QSPI or an SD card to get the HPS going. 

 SD Card: http://www.rocketboards.org/foswiki/documentation/gsrdsdcard  QSPI: http://www.rocketboards.org/foswiki/documentation/gsrdqspiboot  http://www.rocketboards.org/foswiki/documentation/gsrdqspiprogram  You do need to enable QSPI in Qsys, otherwise it will not work. Also, if you use the ByteBlaster on the JTAG, you can program the QSPI within the embedded command shell (steps 6 and 7 here: http://www.rocketboards.org/foswiki/documentation/gsrdqspiprogram). However, I've found using the SD card is a bit easier to start.  Which board are you using? Is it a custom board? The RocketBoards.org site has some pretty good examples on getting some of the dev boards going.

[Altera_Forum]

Hi davidc85, 

I am trying to export the UART0 from the DE1-SoC board to the FPGA but I am unable to determine how to assign the "top level" ports.. ??  As was mentioned, you get the ports for the hps component.. for the UART0 they are as follows in my top level verilog code: // loanio uart0 .hps_0_hps_io_hps_io_gpio_inst_LOANIO61 (<connect to top level>), .hps_0_hps_io_hps_io_gpio_inst_LOANIO62 (<connect to top level>), //  So, I am assuming these need to be assigned to the board pins: "HPS_UART_RX (pin_b25)" and "HPS_UART_TX (pin_c25)" respectively  My question is how you did this? .. in the pin assignents you can't choose these pins as they are reserved? When I compile the project I get the error (for pins B25 and C25): Error (169026): Pin HPS_UART_RX is incompatible with I/O bank 7A. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V. Error (169026): Pin HPS_UART_TX is incompatible with I/O bank 7A. It uses I/O standard 2.5 V, which has VCCIO requirement of 2.5V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 3.3V.   Any help is appreciated, thanks in advance. I have searched and looked for solutions here and this thread was the closest I could find and your reply above mentioned you managed to get this compiled.  other details... Using Quartus etc version 14.0 I know how to make the preloader and linux SD Card.

[Altera_Forum]

Hi Dez74, 

 If you want to use LOANIO61/LOANIO62 for UART0, you can set the "UART0 pin multiplexing" to "HPS I/O Set 1" in QSys instead of routing it to the FPGA. Then you can just route to I/O ports in the top file, and during compilation it will automatically set those pins to B25 and C25.  As for the error (169026), this is due to the HPS_UART_RX/TX pins being set to 3.3V, while the bank is at 2.5V. In the pin planner, set the I/O Standard of these pins to 2.5V.  Marcopoliptica

[Altera_Forum]

Thanks Marcopoliptica. 

 After hours of trying all these different multiplexing options I have got it working ;)  I used to Pin Assignments window to identify the correct GPIO routing for the UART/USB external connector (PIN_B25 and PIN_C25). Both of these are NOT on the loan 61 and 62 but in fact 49 and 50! ... so I used the same LOANIO method and exported 49 and 50 which worked and the fitter assigned them to the desired pins.  61 and 62 would always (correctly) get fitted to PIN_B22 and PIN_G22 respectively, but of course the external connector is physically routed to the above pins.  Thanks again for your help, I can now use the external UART/USB with my softcore processor ;)  RE the voltage error, yes I later realised I just change them from '2.5 V (default)' to '3.3-V LVTTL' and it compiles.

[Altera_Forum]

Please help me! 

 I try to use Loan IO, there are a few issues. What should be the procedure for loading FPGA and HPS work Loan IO? Should HPS configured FPGA? From what source it is necessary to configure the FPGA and HPS?  That in addition Loan IO need to include HPS?  Please share 100% of the working project. For any development board.

[Altera_Forum]

Hello all, 

 Coming from here (http://www.alteraforum.com/forum/showthread.php?t=48691) I'm trying to edit this into my verilog project..  I have built the HPS system, and found, the verilog files. From the verilog file I found three things could be done in the middle, but I don't understand how to get this right..   Do I need to call the hps_0 in my toplevel file? Or is it sufficient to declare the inputs and use them myself? (since the generated verilog file has the input declarations declared, and then calls the HPS_0)  The "hps_io_hps_io_gpio_inst_LOANIO 01..x" do they need to be connected to the pins, (and declared in the QSF pin planning) despite that they are connected to the hardprocessor?   Does the QIP file do anything to configure anything?   Checking in after hrs, Will delve into this again tomorrow (Maybe find the golden formula), but if anyone knows and could save me and future readers some compiler time, Id be very thankfull.

[Altera_Forum]

The loan_io_in, loan_io_out and loan_io_oe conduits are all 66 bits wide to allow for all possible loan I/O signals. I'm only using some of the loan I/O signals though, and I'm setting the bits in loan_io_oe to set the loan I/O signals I use to be inputs or outputs as required, and providing a method of driving my loan I/O outputs and reading my loan I/O inputs. I'm confused about what I should do with the bits in loan_io_in, loan_io_out and loan_io_oe that correspond to the loan I/O signals I'm not using though, as these signals are mapped to peripherals instead of loan I/O - what should I set these bits to?

[Altera_Forum]

Hi, 

 I'm having similar problem. I cannot get to output anything on the pins I loan to FPGA from HPS. I'm just trying to have four GPIO pins and make the LEDs of the HPS on SoCKit board blink. According to the schematic, GPIO 53:56 are connected to the LEDs. When I compile, Quartus is assigning the right pins to these LEDs. But I don't see the LEDs blink.  In the peripherals mux table, there is 'mux_select_1', mux_select_2' and 'mux_select_3'. What is this? What does it do?  Karthik

[Altera_Forum]

Hi, If I may interfere with the discussion... I'm using the DE0-Nano-SoC Kit, and would like to access both HPS CPS CAN1/2 peripherals. The convenient way looks like attaching my CAN PHY to the FPGA expansion pins. Therefore, I need to route the CAN TX/RX HPS pins to existing FPGA I/O. Can I choose which FPGA PIN with be used? Thank you &#128522;Ran

[Altera_Forum]

Hi,  

I try to route HPS CAN1 & CAN2 Peripheral pins over to FPGA I/O, since those are available at the connector. My question is mainly, whether it is possible to pick whatever I/O PIN I desire for the routed HPS CAN PINs (CANx_RX, CANx_TX)...   Thanks!  Ran

[Altera_Forum]

--- Quote Start ---  Thanks Marcopoliptica.  After hours of trying all these different multiplexing options I have got it working ;)  I used to Pin Assignments window to identify the correct GPIO routing for the UART/USB external connector (PIN_B25 and PIN_C25). Both of these are NOT on the loan 61 and 62 but in fact 49 and 50! ... so I used the same LOANIO method and exported 49 and 50 which worked and the fitter assigned them to the desired pins.  61 and 62 would always (correctly) get fitted to PIN_B22 and PIN_G22 respectively, but of course the external connector is physically routed to the above pins.  Thanks again for your help, I can now use the external UART/USB with my softcore processor ;)  RE the voltage error, yes I later realised I just change them from '2.5 V (default)' to '3.3-V LVTTL' and it compiles.  --- Quote End ---     Hi, I know this thread was started long ago. I have same issue as discussed here and need your help with this. I am playing around with the de1 soc board, so I implemented a UART module and need to test it on the board. However, even after following your solution of loaning 49 and 50, I am unable to get it to work. I have LOAN_IO_OE[49] assigned to 1'b0 and LOAN_IO_OE[50] assigned to 1'b1. LOAN_IO_IN[49] and LOAN_IO_OUT[50] connected to RX and TX of the FPGA logic respectively. The TX light (of the UART) on the board does not blink when I execute the logic to transfer via UART. Not sure where the problem could be from. I hope you can help me with this.

[Altera_Forum]

acyril, did you find solution to this?

[Altera_Forum]

Have you got the ARM processor up and running? 

 LoanIO only works if the processor is running because the system control registers must be configured by software running on the processor in order to allow the LoanIO interface to run.  You'll need to generate a design which include the hard processor system with the require LoanIO parameters. From there you will need to generate a BSP and compile a preloader. Once you have the preloader up and running you'll need a simple bare metal program of an infinite loop resetting the watchdog (if enabled) to stop the processor crashing. The preloader will use the BSP information to set the system control registers to the required.  The reason RX works is that the ports default to input which means you can get data in without the processor running. However for TX you need to get be able to set the TX pin to be an output which can only be done once the processor is running.

[SanaGuezguez]

Hello everyone,
I'm having an issue implementing an FPGA to HPS communication and vice versa. I'm using the MitySOM 5csx with a Cyclone V SoC. The purpose of the project is to setup the bridges between the HPS and FPGA in such a way that a program running on the HPS will send data to the FPGA which will process it and return a result. I've generated a QSYS design, composed by the HPS (with Cyclone V settings), two fifos, a clock bridge, a clock and an SDRAM.
When I run the simulation and synthesis and the TCL pin-assignment script generated by Qsys everything works fine. The issue comes when I try to compile the whole design, because I get an error message saying there are 375 IO input pads in the design, but only 331 IO input pad locations are available on the device. I don't know what I'm missing or doing wrong. Any suggestion is welcome