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JSmit123
Beginner
870 Views

How to make altlvds_tx 7:1 LVDS serializer on Cyclone 2 / Cyclone 4E

 

I need to connect Cyclone 2 (I also have Cyclone 4 if it's easier) to LCD panel, which uses LVDS interface (aka FlatLink). What I need to do is serialize 28 bit (plus clock) into 4 LVDS channels (plus clock).

LVDS clock must be 57% duty cycle (57% high, 43% low = 4 bits high and 3 bits low). Clock transition from high to low happens between bit 2 and 3, low to high between 5 and 6.

Here is how it should look:

1100011 <- clock

ddddddd <- 7 bits of serial data channel

 

If it's not clear you can find a picture in datasheet of any LCD panel or flatlink transmitter (for example sn75lvds83)

 

What I was able to do so far:

 

1. Created altlvds_tx with internal PLL, serialisation factor 7, outclock divide factor 7, outclock duty cycle 57. I could not make output clock to transition as required - high to low happens between bit 4 and 5. I guess I could manipulate input data (change it so it appears 2 bits later in lvds stream) - but it looks like unnecessary hack to me. Anyway, I don't want to use internal PLL, since it reserves entire PLL for lvds transmitter.

 

2. I tried to create altlvds_tx with external PLL, however it only has output for LVDS data. Where do I get the LVDS clock? I don't think I can use clock coming out from the PLL, since it appears to be not in phase with the data. 

 

I had an idea to add one more channel to serializer and feed it with constand value 1100011, and use it as a clock, but not sure if it's a proper thing to do (may be too much jitter). On top of this, my data rate is about 7*70MHz and I got the following warning from the Quartus:

Critical Warning (176063): The Transmitter driving I/O pin lvds[0] at data rate 490 Mbps will have degraded duty cycle performance. Maximum data rate for non-degraded duty cycle performance is 311 Mbps.

 

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1 Reply
Rahul_S_Intel1
Employee
68 Views

Hi, I am suggesting to try on the Cyclone 4 FPGA for the the above configuration. Regards, RS
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