Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19345 Discussions

MAX10 Soft-LVDS creates TimeQuest warnings

SZand
Beginner
962 Views

I am using the Soft-LVDS on 10M16SAE144 with external PLL, the LVDS pins are located in Bank3 (pins with full LVDS support)

TimeQuest show some warnings regarding not fully constrained output paths and output pins. All warnings have to do with the LVDSp/n pins.

  • How to full constrain the Soft-LVDS outputs?
  • Because the LVDS-outputs will be direct connect to the Soft-LVDS macro there is no need for constraining, isn't it?

Thank you for help.

0 Kudos
2 Replies
Rahul_S_Intel1
Employee
165 Views
Hi , When you select the Altera LVDS serdes IP you have use the timing constraints . The timing constraints can be done using timing analyzer tool or SDC FILE. Regards, RS
SZand
Beginner
165 Views

Hi,

thank you for your answer, although this dos not help me very much.

I have found that the output LVDS pins of the device are hard coded to the Soft-LVDS macro and threfore no timing constrains are neccessary. But when using the "set max_skew cmd (from inputclk to all LVDS-pins) the warnings gone away.

Reply