How to migrate cycloneV's project to stratix10

[china_cn]

The CycloneV device I am using is of designation 5CEFA9F31I7 and the quartus version I am using is 18.0. The Stratix10 device used is 1SX085HN2F43E2LG, and the quartus version is Pro 21.3.

Since a large number of IP cores from LPM libraries such as LPM_COUNTER, LPM_SUB_ADD, and LPM_COMPARE are used in the CycloneV project, they are not found in quartus Pro 21.3. How should I solve this problem.

Pls if there is a suitable way to quickly migrate the project.

Thank you for your answer

[YuanLi_S_Intel]

Hi, i think you need to reinitiate the IP in Stratix 10 since both cyclone v and stratix 10 are different.

[china_cn]

But for things like ALT_ADD_SUB and ALT_COUNTER and so on, I don't seem to find them in the IP Catalog, how these IP cores should be configured.

Thank you

[china_cn]

Can someone answer my question? How do I implement LPM_COUNTER and signed LPM_ADD_SUB in stratix10 devices

[YuanLi_S_Intel]

Understand. If the IP is not available in the IP catalog, it is not supported. However, user can get the logic RTL code from the template and then paste it into the new quartus version.

https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/design/ted/ted_com_insert_template.htm

[china_cn]

This doesn't seem to be the answer I was looking for. My concern is that using RTL to implement LPM_ADD_SUB will not get satisfactory performance. Because I can see from Technology Map that when I need to latch two clocks, the structure produced by these two methods is completely different.

[YuanLi_S_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[sstrell]

Can you show your code?  Why are you latching (gating?) clocks?