The CycloneV device I am using is of designation 5CEFA9F31I7 and the quartus version I am using is 18.0. The Stratix10 device used is 1SX085HN2F43E2LG, and the quartus version is Pro 21.3.
Since a large number of IP cores from LPM libraries such as LPM_COUNTER, LPM_SUB_ADD, and LPM_COMPARE are used in the CycloneV project, they are not found in quartus Pro 21.3. How should I solve this problem.
Pls if there is a suitable way to quickly migrate the project.
Thank you for your answer
Understand. If the IP is not available in the IP catalog, it is not supported. However, user can get the logic RTL code from the template and then paste it into the new quartus version.
This doesn't seem to be the answer I was looking for. My concern is that using RTL to implement LPM_ADD_SUB will not get satisfactory performance. Because I can see from Technology Map that when I need to latch two clocks, the structure produced by these two methods is completely different.
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