How to protect CPLD from power transients? Programming is being corrupted

[Rh11]

Hello,

How to protect CPLD MAX V (5M570Z) from power transients?

Programming is being corrupted on several boards.

The board worked fine with previous power supply models (it had a capacitor bank for filtering, 72mF), but the current power supply has a different circuit (no capacitor bank, and possibly some noise is being passed on to the boards).

Is there a pin that can be kept biased, such as pull-up or pull-down, to prevent accidental reprogramming?

The board has a JTAG connector, but it is left open. Could I leave some connection on the JTAG port to protect the programming?

Thank you.

[_AK6DN_]

"The board worked fine with previous power supply models (it had a capacitor bank for filtering, 72mF), but the current power supply has a different circuit (no capacitor bank, and possibly some noise is being passed on to the boards)."

Fix your power supply issues. You can't expect the CPLD to work with an unreliable power supply.

[Rh11]

Thanks, but I only have easier access to the boards. The power supply is new, and although there have been some defects, it should not be possible to modify it or add filters internally, due to the physical occupation of the internal area. The circuit that was microcontrolled in other versions was discretized, so it had greater internal occupation.

[_AK6DN_]

The MAX V device stores is program in its configuration flash memory. At power up, the device copies the contents of the
CFM to the SRAM configuration array scattered around the device that programs the logic to act as you have specified.

If there are power transients, those SRAM cells can be disturbed, corrupting the device program.

The CFM contents should still be ok, but the copy of the program copied out across the device has been corrupted.

So until you address the unreliable power supply issue you can't prevent the SRAM cells from being corrupted.

You have limited options if you cannot change the external power supply:

(1) add bulk capacitors and high frequency filter capacitors directly around the CPLD device to provide local power stability

(2) if the above is not adequate, add a local 1:1 local power supply to stabilize the unreliable supply you have.

As I said, until you address the power instability problems fiddling with pullups around the device is going to be a crap shoot.

[Rh11]

I found something for MAX 10, I don't know if it is applicable for MAX 5 since there are 3 ICs in the same connector, they appear in series in the programmer

https://www.intel.com/content/www/us/en/docs/programmable/683865/current/jtag-configuration-setup.html

[Farabi]

Hello,

I recommend to check your power rails with oscilloscope during power ramp up. You might find something that could related to the root cause of your issue.

regards,

Farabi