How to reduce the high fan out nets in Quartus project?

[BXia]

Hi Intel FPGA supporter, We found there are high fan out nets in our project, is there any way to reduce the high fan out nets? Please see the attached image. Thanks in advanced!

[sstrell]

There are many methods for reducing high fanout.  Register duplication is usually the main solution.  Lots of resources available for this:

https://www.intel.com/content/www/us/en/docs/programmable/683641/24-2/duplicate-registers-for-fan-out-control.html

https://learning.intel.com/Developer/learn/courses/216/design-evaluation-for-timing-closure

https://learning.intel.com/Developer/learn/courses/237/best-design-practices-for-timing-closure

[KennyTan_Altera]

Most importantly, you will need to verify if the settings have taken effect in the design. You can do this by checking the report for the duplication of registers to reduce fan-out. Note that duplicating fan-out will not impact functionality, as the duplication is done in parallel rather than in series.

[BXia]

Hi @sstrell and @KennyTan_Altera ,

Thanks for your advice.

We will try to check this, do you know if there is any command we can execute in Quartus directly to find and duplicate registers automatically?

Thanks again.

[KennyTan_Altera]

Here is the steps:

1. Open the Quartus Prime Tcl Console.
2. Run the following command:

TCL

1

report_register_duplication -panel_name "Register Duplication Report"

[sstrell]

That's to report on register duplication, not perform it.

See the document and trainings I pointed you to.  There are many ways to do this.  Of course, doing it in your code gives you the most control over what gets duplicated and how many times.

[KennyTan_Altera]

Yup, reporting is the later part after you duplicate the register as pointed in the training material.

[KennyTan_Altera]

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