How to reset a ram?

[Altera_Forum]

Hi, 

in my vhdl design I got a ram signal R then I try to test it against A with "if A > R then..." but R starts with a 'X' value so the test is not working. What could I do to solve that problem? Thanks.

[Altera_Forum]

--- Quote Start ---  Hi, in my vhdl design I got a ram signal R then I try to test it against A with "if A > R then..." but R starts with a 'X' value so the test is not working. What could I do to solve that problem? Thanks.  --- Quote End ---    for power up conditions look at section 3-14:  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram_rom.pdf  for reset, you can only reset output ram registers if available

[Altera_Forum]

As I'm using M9K I know the signal is starting at 0 but Modelsim doesn't know and says it's X. Is there a way of making the simulation start with 0?

[Altera_Forum]

--- Quote Start ---  As I'm using M9K I know the signal is starting at 0 but Modelsim doesn't know and says it's X. Is there a way of making the simulation start with 0?  --- Quote End ---    if you are looking at your registers at ram output then initialise them, otherwise ignore the x until it is driven from write side

[Altera_Forum]

--- Quote Start ---  As I'm using M9K I know the signal is starting at 0 but Modelsim doesn't know and says it's X. Is there a way of making the simulation start with 0?  --- Quote End ---    But you dont know the ram will start up at 0 (memory contents at startup will be random unless specified). Hence why you get an X in simulation - ie unknown. You need to write something to the address to get a known value.

[Altera_Forum]

How to tell my vhdl design to ignore X?

[Altera_Forum]

--- Quote Start ---  How to tell my vhdl design to ignore X?  --- Quote End ---    If you do that, you're likely to break the design on the FPGA. Basically, fix your testbench so that something is written to the ram before you start, or give the ram an initial startup value via a .mif file. Or you could infer the ram and set the initial contents with a function.

[Altera_Forum]

--- Quote Start ---  If you do that, you're likely to break the design on the FPGA. Basically, fix your testbench so that something is written to the ram before you start, or give the ram an initial startup value via a .mif file. Or you could infer the ram and set the initial contents with a function.  --- Quote End ---    I don't see how a proper design would break as such.You read from ram what you have written to it. If you read before write then your approach is wrong. If you pass ramoutput to accumulate then start after the x.

[Altera_Forum]

--- Quote Start ---  I don't see how a proper design would break as such.You read from ram what you have written to it. If you read before write then your approach is wrong. If you pass ramoutput to accumulate then start after the x.  --- Quote End ---    It depends on your approach. If you put in code to detect and ignore 'X', the synthesisor can use that as a "dont care" state and may minimise your logic in a way you didnt intend. Its much safer to allow Xs to propogate as it makes errors easier to detect.

[Altera_Forum]

To reset the RAM in modelsim to get rid of x you could use the mem load command: 

mem load -filltype value -filldata 0 -fillradix symbolic /tb/the_ram_to_be_resetted/altsyncram_component/m_default/altsyncram_inst/mem_data  or emulate random data: mem load -filltype rand -filldata 0 -fillradix symbolic /tb/the_ram_to_be_resetted/altsyncram_component/m_default/altsyncram_inst/mem_data  In a real design you need a memory initialization file. If not supplied or not found Quartus sets all initial values to 0. This behaviour is may depending on the type of FPGA.

[Altera_Forum]

--- Quote Start ---  To reset the RAM in modelsim to get rid of x you could use the mem load command: mem load -filltype value -filldata 0 -fillradix symbolic /tb/the_ram_to_be_resetted/altsyncram_component/m_default/altsyncram_inst/mem_data  or emulate random data: mem load -filltype rand -filldata 0 -fillradix symbolic /tb/the_ram_to_be_resetted/altsyncram_component/m_default/altsyncram_inst/mem_data  In a real design you need a memory initialization file. If not supplied or not found Quartus sets all initial values to 0. This behaviour is may depending on the type of FPGA.  --- Quote End ---    The code the OP has posted indicates the ram is already initialised to 0. The Xs are likely the results of code problems elsewhere.