How to resolve timing violations in the accumulator?

[student8]

My counter has been split into a combination of 2 16-bit counters, ultimately achieving a 32-bit counter. The recommended method by Quartus is to insert a pipeline between different bits of the counter. I think this method is very inconvenient to implement. What are the good solutions?

Time  analysis is shown in the figure。

This is the result of post fitting.

[sstrell]

See my reply in your older post.  Something is fishy here with your adder.

[_AK6DN_]

I agree. The timing report shows at least a nine level CIN/COUT ripple carry chain.

If you want to go for high speed, you need to implement a carry lookahead adder design.

The design as implemented is not going to run very fast due to the implementation.

[student8]

Thank you for your reply. The performance has improved after switching to a carry-lookahead adder.

[RichardTanSY_Intel]

Kindly share your design by archiving the project (Project > Archive Project) so that I can investigate it further.

Regards,

Richard Tan

[student8]

Thank you for your response. I'm sorry, but the rest of the code is not my work, and I cannot share it. I can only provide my work, which is the "timedelay" file. 

[RichardTanSY_Intel]

I believe the suggestion provided by the community have help you improve timing.

Do you need any further assistance in regards to this case?

Regards,

Richard Tan

[RichardTanSY_Intel]

I believe your inquiry has been answered. Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan