How to set analog delay MaxPlusII

Altera_Forum · ‎11-04-2008

Hi,

I need to set a delay following a rising_edge of a sig_a.

In order to do that, I have utilized the:

c<=sig_a;

x <= c after# nS; -- where I can select the# through a data on the bus.

I don't know what I am missing, but simulating that the signal is always delayed by the same delay=8nS...

I wrote the number directly in case of same "conflict" but the result is the same.

Following instruction (that is like a "pulse with modulation") is always = 0...

z <= sig_a and x;

Could you please help me to generate a pulse with a variable width?

Or, what is the way to stop the optimizer in order to avoid to remove the series of Not?

Thanks a lot for your help.

Altera_Forum · ‎11-05-2008

The VHDL analog delay statements are usable for simulation only. I think, this simple fact is mentioned in any serious VHDL textbook. The reason is simple as well: Programmable logic has no suitable hardware to generate delays. The usual way is to generate them synchronously between clock edges.

Generating short and adjustable delays in FPGA or CPLD isn't that easy. A CPLD has no PLL to multiply the input clock to e. g. 500 MHz that allows 1 or 2 ns delay steps like a FPGA does.

I understand from your post, that you also tried to use logic cell delay lines. If I remember right, MaxPlus II does not generally remove redundant logic cells in synthesis. Quartus in contrast does, but you have synthesis atributes to define precisely which logic cells should be kept in synthesis. I'm not sure about MaxPlus II support of synthesis attributes, thus I suggest to use Quartus, if you find no means to define delay lines in MaxPlus II.

You should be aware, that you are leaving the straight way of synchronous logic synthesis with the delay chain approach. You should know, what you re doing and probably have to ignore some compiler warnings.

Altera_Forum · ‎11-05-2008

Thanks for the reply.

I tried with Quartus web edition, but I have the same result...

VHDL compiler recognize the "after" keyword, but I see want gnerate any delay, my question is why it is anable that?

Anyway, is there a way to insert a "chain" of buffer in order to obtain a delay by 1nS? I don't need to be precise, I mean +/- 1nS is OK too.

I wrote below code, but simulator doesn't show any "pulse" (should I change the quartus default one?)

a <= sig_in;

b <= not (not a);

c <= b;

d <= not (not c);

x <= b and not d;

Thanks for your help.

Altera_Forum · ‎11-06-2008

If you add your delay with buffers it may vary with temperature.

If you explain more about why you need to delay something for such a short time as 1 ns it will be easier to assist you. Is there anyway you can get around using a delay? Can you delay it with a register for 1/fmax s? What fmax do you have in your system?

Best Regards,

Ola Bångdahl

Altera_Forum · ‎11-06-2008

I mentioned the basic method in my previous post, it' by synthesis attributes.

The syntax is documented in the Quartus manual, it's basicly like below

signal my_wire: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of my_wire: signal is true;

You can expect to need about 4 or 5 logic cells per 1 ns delay with Cyclone III FPGA, the MAX II value should be similar. For a compact coding, you can apply the synthesis attribute to a std_logic_vector rather than individuals signals.

Altera_Forum · ‎11-06-2008

Thanks for ur reply,

I tried that statment yesterday while reading the manual, but simulator is not showing any delay.

I believe is due to the standard simulator I am utilizing, and I think I should utilize the post fitting one (verilog?). If so I need to ur help in picking and setting that because from the manual I am still not able to make it working (error with "executable" file not found???, this simulator is not so intuitive...).

CPLD I am utilizing is a EPM7128-10 and f=100Mhz.

code I wrote is below... but it doesn't show any "pulse", could you help?:


library ieee;
use ieee.std_logic_1164.all;
entity analog_delay is
port(
	sig_go: in std_logic;
	sel: in std_logic_vector(2 downto 0);
	z: out std_logic
);
end analog_delay;
architecture delay_ns of analog_delay is
	signal a,b,c,d,e,f,g,y: std_logic;
	attribute syn_keep: boolean;
	attribute syn_keep of a,b,c,d,e,f,g: signal is true;
begin
	sel_delay: process (sig_go,sel,a,b,c,d,e,f,g,y)
	begin
		-- delay input signal
		a <= not(not(not( not sig_go)));
		b <= not (not a);
		c <= not (not b);
		d <= not (not c);
		e <= not (not d);
		f <= not (not e);
		g <= not (not f);	
		-- mux select delay_ns
		case sel is
			when "000" => y <= sig_go;
			when "001" => y <= a;
			when "010" => y <= b;
			when "011" => y <= c;
			when "100" => y <= d;
			when "101" => y <= e;
			when "110" => y <= f;
			when "111" => y <= g;
		end case;
		
		-- results: pulse
		z <= sig_go and (not y);
	
	end process sel_delay;
end delay_ns;

Thanks a lot for ur help and contribution in making it working...

Altera_Forum · ‎11-07-2008

I am simulating the above code, but compiler is warning for:

--- Quote Start ---

Warning: Design contains 4 input pin(s) that do not drive logic

Warning (15610): No output dependent on input pin "sig_go"

Warning (15610): No output dependent on input pin "sel[0]"

Warning (15610): No output dependent on input pin "sel[1]"

Warning (15610): No output dependent on input pin "sel[2]"

Warning: No paths found for timing analysis

--- Quote End ---

Analyzing it with Modelsim-altera... no changes on output while changing sig_go.

Pls, could you help?

Thanks

Altera_Forum · ‎11-07-2008

I found, that keep synthesis attribute is ignored with EPM7000 devices (and probably other simple CPLD). I had tried with MAX II before, which works O.K. There may be other techniques to achieve the intended behaviour with EPM7000, but I didn't use these devices since about 10 years and can't help in detail.

Altera_Forum · ‎11-08-2008

Is there another way to get that?

I believe that quartus (better than max) should have a similar way to skip the optimization...

Thanks for u all help...