Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

How to set the Sample Frequency of the Altera Modular ADC core

Altera_Forum
Honored Contributor II
‎03-01-2016 01:38 AM
1,100 Views

When running 5_ADC_LAB/ADC_Streaming_Lab in the ADC Toolkit from Arrow MAX 10 FPGA Evalution Kit, I notice that 

the Sample Frequency is 250,000 while the snapshot in the document is 500,000. 

 

Where and How to change the ADC Sample Frequency in the Quartus/Qsys?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.