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How to set timing constraint for differential signal?

XQSHEN
Novice
212 Views

For example, clk_p, clk_n

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1 Solution
SyafieqS
Moderator
173 Views

Hi Shen,


Only the clock_p of the differential ports needs to be constrained.


If both are constrained, the tool will take them as two separate clock definitions and analyze inter clock paths between them.

This can lead to incorrect requirements.


Similarly, only the P-side of the differential data port needs to be constrained in the input delay and output delay constraints.

The analysis of the clock_n is exactly the same as the clock_p


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3 Replies
XQSHEN
Novice
190 Views

should I use one of them to set timing constraint or both of them?

normally how to write sdc for such signal?

SyafieqS
Moderator
174 Views

Hi Shen,


Only the clock_p of the differential ports needs to be constrained.


If both are constrained, the tool will take them as two separate clock definitions and analyze inter clock paths between them.

This can lead to incorrect requirements.


Similarly, only the P-side of the differential data port needs to be constrained in the input delay and output delay constraints.

The analysis of the clock_n is exactly the same as the clock_p


SyafieqS
Moderator
154 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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