Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21144 Discussions

How to simulate PCIe and DDR in ModelSim

treble99
New Contributor I
1,966 Views

Hello,

 

  I am reposting, in a new thread as suggested to me.

I am trying to simulate PCIe_DDR4 example provided for Terasic DE5a-NET DD4. I have made a modification to the project. After opening it in Quartus Prime Pro [linux: 22.4.0] and going to Platform Designer [22.4 Build 94] I add a custom counter logic as a component and an Avalon FIFO [altera_avalon_fifo] in the System Viewer. Just the counter and the FIFO together were simulated in ModelSim and found to be working correctly.

The Avalon FIFO will connect to the pipe stage [altera_avalon_mm_bridge]  and write data to the DDR4 memory. I want to verify this in simulation before proceeding to hardware verification.

I am unclear as how to do this and would appreciate any recommendations. How can I simulate an environment where My Counter input is going through the FIFO and being written down to the DDR memory? The PCIe_DDR4 example has several ip blocks:

altera_pcie_a10_hip

altera_avalon_pio

altera_avalon_mm_bridge

altera_emif

I would like to inspect signals through these IPs and confirm read/writes happening correctly.

Please let me know if you would require any more information?

 

 

0 Kudos
9 Replies
Wincent_Altera
Employee
1,929 Views

Hi,

 

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

 

Best regards,

Wincent_Intel


0 Kudos
Wincent_Altera
Employee
1,909 Views

Hi,


Just wondering if are you still using AN708 as per mention in the previous forum case ?

If yes my advise will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system.


Regards,

Wincent_Intel


0 Kudos
treble99
New Contributor I
1,907 Views

Hello,

 

   I opened this thread as recommended for the simulation process.

Can you please explain how I would be able to generate the testbench for the system. What steps should I take?

Thanks!

0 Kudos
Wincent_Altera
Employee
1,880 Views

Hi,


Unfortunately, it might not be the answer that you looking at.

But I have to let you know that the AN708 is for hardware test only, not for simulation.

But if you need to run Arria 10 simulation you may refer below step to generate the test bench

Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide".


Detail you may refer to link before.

https://www.intel.com/content/www/us/en/support/programmable/articles/000092687.html


Regards,

Wincent_Intel


0 Kudos
Wincent_Altera
Employee
1,867 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


0 Kudos
treble99
New Contributor I
1,853 Views

Hello,

   I am going through the user guide you provided.

To clarify the Terasic DE5a-NET DD4 has an Intel Arria 10 GX FPGA (10AX115N2F45E1SG). Therefore I should be able to perform simulations in ModelSim, correct?

The user guide has instructions on generating testbenches. I am trying to implement them, I will get back to you soon.

The user guide was not that informative on how I could provide stimulus/input to the design through testbench scripts.


Thanks!

0 Kudos
Wincent_Altera
Employee
1,799 Views

Hi,


You can generate the example design via "IP catalog"

Once you generated the design, the folder will be available.

Please ensure you select the simulation tools while generating the HDL.


Regards,

Wincent_Intel


0 Kudos
Wincent_Altera
Employee
1,767 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


0 Kudos
Wincent_Altera
Employee
1,738 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

 

Regards,

Wincent_Intel


0 Kudos
Reply