How to simulate the FPGA neural network in Altera

[Altera_Forum]

I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device? 

And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...

[Altera_Forum]

Fixed Point toolbox has some automatic capability. I don't use it, but you can google how to. It is easier to just right click individual blocks and set their data types. You should know the range of outputs each block can produce.

[Altera_Forum]

Can I selct the whole scheme and aplly Fixed point toolbox? I think Matlab 2009 shuld have this capability. 

I really have no time despite I am at one step to transfer my design in HDL. So it would be fine to see the hdl simulation at list in DSP, ModelSim or at the best the Xilinx. What I need for the last option? And what ranhe should I know--I have some input that has value so I need at first moment to show k biggest inouts at outputs, that should be above 0. And in my Simulink wave I see the decresing line--could I see it in HDL simulation--and what kind of wave I would see in the whole?

[Altera_Forum]

You should be able to apply Fixed point toolbox to the whole design. I would be careful of multiplication operations since you can reach overflow or saturation easily if you dont have enough bit width. Once you generate your HDL you can import it into Modelsim. You should also write a quick verilog testbench to simulate some inputs. Technically you should see the same waveforms in modelsim as you see in simulink if you use the same inputs.

[Altera_Forum]

"if you dont have enough bit width" -- when it can happen and how to check it. What bitwidth could be of these inputs? And when this overflow and saturation happen? Ypu warn abot Gain block in multiplication -- this koeficient could be really very different from current 20 up 2000 and more. 

"generate your HDL you can import it into Modelsim" and what options I also should apply for verilog file -as I have generated such file from Simulink floating points. even in Filter Design Coder. "You should also write a quick verilog testbench to simulate some inputs" -- what it means. What is Testbench --there is no HDL verifier in Matlab2009a, what is testbench (ModelSim?), and why I shoudl simulate just some inputs -- I need to use all of them -- in outputs I could use just K. If I would have enough time and Generated Fixed point Simulink could you use it in DSP Bloclset with wave results and hDL in ModelSim?

[Altera_Forum]

If you don't have enough bit width then your values would saturate. This means, say your range is 0 to 32, but your block wants to output 100. This would be an issue since this value is beyond the ranges that is allowable by your bit width. That means that the block would peg at 32, and will output the wrong value. You need to know what your Gain is and what values each block can output so that you can properly set your bit widths. 

 A testbench is a simulation file that you can write in verilog or vhdl. Here you can set up your clock, reset, and inputs. Read about writing testbenches online.  The file sinmulink44_dig2009a.mdl that I attached is already configured to use the fixed point toolbox.

[Altera_Forum]

Yes I can use F.P.ToolBox with 2009a version but designer just with 2013. 

But when I generated Verilog code by HDL Coder (or Filter) -- why and how difficult I should create testbench. Shoud I do it manually, can I exclude such file of my simulation and could I do it automatically f.e. in DSP, Model-Sim as the Xilinx System Generator has such functionality -- as seems to be. http://www.mathworks.com/help/dsp/examples/generate-hdl-code-for-programmable-fir-filter.html -- here seems no mentioning of F.P. Toolbox and Testbench And very important question -- when I choose Modelsim design files -- there is no files or the whole list that has its sub-parts what I should use if I have generated the hDL file?

[Altera_Forum]

www.physi.uni-heidelberg.de/~angelov/vhdl/vhdl_ss09_teil05.pdf  

www.tech.mtu.edu/nsfate/spring2013workshop/lab%20files/lab%204%20-%20testbenching.pdf - Really have no time to learn it.

[Altera_Forum]

So what about HDL testbench. How difficult is it to do it manually? Could I do it automatically? 

In Altera, ModelSim, DSP? System Generator seems to have. but I really have no time to download the last and is it possible to use it without Xilinx FPGA?

[Altera_Forum]

The HDL testbench can be made by hand. It is simply 1 file that instantiates your design, and sets up the clock, resets, inputs and outputs. If you have the basic, free, version of Modelsim all files have to be written in the same language. So DSP builder outputs VHDL, therefore you testbench has to be in VHDL. This is a pain... for me at least because I'm much better in Verilog than VHDL. 

 But before you do the testbench, were you able to make your HDL files from the digital version of the neural net design?

[Altera_Forum]

Just now I opened FP toolbox in MAtlab 2009a but really it is diffuclt to grasp 

hwo to make automatical conversion to Fixed Point? If I should do it by hand HDL testbech -- are there ready example that I would cahnge a bit for my task --how much number of lines I should wright? And I should present my work in 2-3 days so I want to present also the digital version taht i got in Simulink-- in Altera or Xilinx. The last think is very valuable there.

[Altera_Forum]

So what exactly do you want me to do? I can generate you the DSP model and the VHDL code from that... but you won't learn anything in the process.

[Altera_Forum]

I would try to do it by myself but have no time particularly for VHDL testbench. 

Untill tomorrow I would like to have the HDL realization of my simulink design to show it on my presentation -- especially it would be fine to see on Xilix, despite other options would be good. Then I will try to do it be myself.

[Altera_Forum]

And I also am better at least theoretically in Verilog and it is prefferable

[Altera_Forum]

http://www.alteraforum.com/forum/attachment.php?attachmentid=10775&stc=1 I think if you would provide FPGA wave (signal) of this circuit it would helpful not just for me but also for those people that would see my presentation. I have said a few of them have skills in Xilings so they value it enough. Then I would by myself created the testbench for another case or in another language and produced here. It is even interesting here. Despite the image of disrete signal show me a few about nature of the sognal -- for example why all waves in this signal is the same level -- what they shows --a how display decreasing signal like in Simulink?

[Altera_Forum]

Since I found this project pretty interesting, I'm going to provide you with the generated vhdl code. It is up to you to figure out how to use it, and how to build the testbench and modelsim simulation. 

The code is for 1 Winner Takes All neural net with 6 inputs. If you want more than 1 winner, then you would have to regenerate the vhdl on your own. The DSP builder model is also attached.

[Altera_Forum]

http://www.alteraforum.com/forum/showthread.php?p=92866 http://www-mtl.mit.edu/courses/6.111/labkit/simulation.shtml -- here is about modelling testbench (despite the first item is not very understandable). Is it really automatically to make testbecnh in Verilog or at least in VHDL in ModelSim. And what WTA net you included, what is its algorithm? I need to realize my olgorithm. And one important question -- can I simulate my algorithm in Xilinx System Generator? If so -- what part of Vivaro I need to download -- as the whole bunch of 5gb is to much -- but is it possible to use just needde for HDL generated code simulation?

[Altera_Forum]

The VHDL testbench is very simple to write. It's 1 file and few lines of code. Here is a guide: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html 

 The WTA net is the same algorithm as in the simulink files set for 1 winner and 6 inputs. The VHDL code was generated using DSP builder. If you have Quartus, then you also have Altera's version of ModelSim. You just need to start a project in model sim and drop in the VHDL files and your testbench. Make sure your libraries are properly set up.  I can't help you with Xilinx b/c I don't use Xilinx. This code probably won't run in with Xilinx tools b/c it is generated based on Altera's libraries.

[Altera_Forum]

But it is example on VHDL. It would be better to write in Verilog.  

From another hand -- I was found a lot of files about Verilog testbench -- but it is not so easy to undestand despite I was theoretically accustomized in Verilog. And I do not understand why when i converted my simulink design (despite not converting in fixed point) I have got abou 6-8 thousands lines of verilog code? And if it is so simple, despite you have written otherwise above, what is rule to apply this testbench -- why clock should be apply here -- to what component of circuit it should apply--should it be once-- then what is the role of reset--shoud it apply for every "clock" when one of two different of wires go inside integrator (with minus or plus values; 0 value is final third condition when system is optimized) -- I am not very awares of these features of digital circuits. And if I pass for input such values 2,5, 7, 11, 14..what types of input I should use. Shoudl it be 4-bit as 14 is 1110, then I multilpy for 20 --should I use n-bit for 280. And of kind of output I should use --just the 1 as winner and 0 for other types?

[Altera_Forum]

Everything you asked has been answered in this thread, but I'll explain again: 

 1) Modelsim does not allow mixing of languages (on a free license), therefore since the DSP code is in VHDL, the testbench also has to be in VHDL.  2) Your conversion may be different because you were using HDL coder, while I used Altera's DSP builder. The code i got is about 1.3k lines.  3) in the testbench you set up your clock, resets and inputs: the clock I used was 500kHz. The reset is used to initialize values in synchronous processes. Since the DSP builder code is set for an active high reset, you must keep the reset high for at least 1 clock cycle, and then bring it low. The other inputs include valid, channel, and the 6 data inputs. The Valid signal is high (1) every 5 clock cycles in my design. This allows for the integrator loop to process before new data comes in. The channel input is always 0, we have 6 simultaneous inputs, no data is being multiplexed. The 6 inputs are your data.  The VHDL code I provided includes the whole NN. All you need to do in connect the inputs, the clock (only 1 clock is used), and the reset and then look at the outputs.  4) My circuit is a 1 winner takes all - therefore only one of the outputs will be > 0. The inputs are set to 12 bit values. Therefore 14 is "000000001110". If you use 4 bit values, you can only input values <16. Using 12 bit you can use values <2^12

[Altera_Forum]

Oh, I understand the wave charts can just produce the signal of level of 1 or 0 so here is no nesessity to use comparator to transform the n>0 to 1 and m<=0 to 0. But is it impossible to show the decerasing for example the initial signal from 7 to 2 with almost linear decrease and then with horizonal line of final level? 

Then could you explain what is the role of clock, reset? What is difference? What influence one and what the other. Which influence the integrator discrete addings (how find the integrator code in HDL generator), and what RESET reset?

[Altera_Forum]

Yes you can see the decreasing signal in the wave chart by changing the "Format" from "Literal" to "Analog". It will display a plot instead of showing actual values. 

 Clock is the system clock of the design. In FPGA designs everything is synchronized to the rising edge of a clock. In this case the system clock is 50kHz (20000 ns period). Then there is the "Valid" signal. This states when new data is coming in. In this design it is set to 10kHz. So every 5 clock cycles, the design logs new incoming data. This is done so that internal portions of the design (like the integrator) can complete their arithmetic loops before new data comes in. The "Reset" signal is used just initially to set everything to 0, otherwise some outputs (like multiplier outputs) can initialize with unknowns ("X") and propagate Xs through the design.  If you open up the zip file, it includes the simulink file using DSP blockset. You will see that the integrator is described using discrete blocks: a delay (z^-5), adder, multiplier, because a discrete integrator is of the form: Y(z) = T*X(z) + z^-1 * Y(z)  (I use z^-5 because sample delays refer to system clock - 50kHz - while my data rate is 10 kHz. The integrator delay in the equation above is referenced to the data delay).