How to solve this warning

[Altera_Forum]

hello,everyone, 

Here are several Warnings of my design, I list below, and how to avoid these warnings? 1-   --- Quote Start ---  Warning: (10273) Verilog HDL warning at FLM_CTL.v(100): extended using "x" or "z"  --- Quote End ---   2-   --- Quote Start ---    Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[2] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[0] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[3] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[1] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[4] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[5] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[6] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X Warning: Latch RGBDisplay:uDispModule|PRE_FLM_READ_DATA0[7] has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal RESET_X   --- Quote End ---     the first warning because the following code:   --- Quote Start ---  assign FLM_DATA = (!RESET_FLM)? 16'bz:  (FLM_RW_SEL == 1'b0)? FLM_DATAIN:  16'bz;   --- Quote End ---   FLM_DATA is the a 16bit width biderection Bus, i define it with "inout" type. so when I read data i need to set the FLM_DATA to "z", FLM_DATAIN is the data to write, RESET_FLM si reset signal, FLM_RW_SEL is a another control signal.   The Verilog code relavant to the second warning is below:   --- Quote Start ---  reg [15:0] PRE_FLM_READ_DATA0; assign PIC_DATA = (BUS_W == 3'd4)? {PRE_FLM_READ_DATA1[7:0], PRE_FLM_READ_DATA1[15:8], PRE_FLM_READ_DATA0[7:0]}:  (BUS_W == 3'd3)? {6'd0, PRE_FLM_READ_DATA1[7:2], PRE_FLM_READ_DATA1[15:10], PRE_FLM_READ_DATA0[7:2]}: 24'h0;   --- Quote End ---   PRE_FLM_READ_DATA1 is the same to PRE_FLM_READ_DATA0 PRE_FLM_READ_DATA1, PRE_FLM_READ_DATA0 update:   --- Quote Start ---  always @(FLM_READ_DATA or RESET_X) begin  if (!RESET_X) begin  PRE_FLM_READ_DATA1 <=# P_DLY FLM_READ_DATA;  end  else if( FLM_READ_ADD[0] == 1'b1 ) begin  PRE_FLM_READ_DATA1 <=# P_DLY FLM_READ_DATA;  end  --- Quote End ---   i dont know how to avoid these warnings? Can I pay no attention to these warnings?   I respect you reply, thank you!

[Altera_Forum]

Hi, 

 How about using {16{1'bz}} or 16'bzzzzzzzzzzzzzzzz instead of 16'bz?  For the second warning, altera doesn't recommend to use latches. You really need one?  Thanks

[Altera_Forum]

--- Quote Start ---  Hi,   How about using {16{1'bz}} or 16'bzzzzzzzzzzzzzzzz instead of 16'bz?   For the second warning, altera doesn't recommend to use latches. You really need one?   Thanks  --- Quote End ---   i need to keep the value .if not use the latch, what can instead? thank you

[Altera_Forum]

and always this warning:Warning:  

  --- Quote Start ---    Verilog HDL Always Construct warning at RGBDisplay.v(482): variable "PRE_FLM_READ_DATA1" may not be assigned a new value in every possible path through the Always Construct. Variable "PRE_FLM_READ_DATA1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.   --- Quote End ---   what should i do?

[Altera_Forum]

thanks gee, the first problem is managed.

[Altera_Forum]

Hi, 

 Of course, the ff is the better way to hold value than the latch. If you need latches, you should read quartus II handbook vol-1 section II-6 latch and may ignore the warning.  Thanks

[Altera_Forum]

One way to not use latch, but use DFF in order to keep a signal is that to use the ENABLE input of the DFF. 

 You should manage a logic that move your enable at the istant you wanna "latch" your data. Of course your input signal shall be sampled at the same clk of the DFF you wanna use.