How to start with Quartus 2014.2?

[Altera_Forum]

Hello, 

 Maybe the title is not clear. Let me explain more.  I have recently downloaded and installed the free version of Quartus 64 bit 2014.2 for Windows. Then, I opened a .VHD file. Quartus now opened VHD file successfully.  Now I want to Analysis and Elaboration, then use State Machine View, but all of these buttons are grey (so I cannot press them).  What should I do now?  Thank you very much,

[Altera_Forum]

First of all, Quartus 14.2 doesnt exist. Are you sure it's not Q14.0? 

 Secondly - you need to create a project before you can run those tools

[Altera_Forum]

Sorry, it is my mistake. 

 yeah, I mentioned version 14.0

[Altera_Forum]

--- Quote Start ---  First of all, Quartus 14.2 doesnt exist. Are you sure it's not Q14.0?  Secondly - you need to create a project before you can run those tools  --- Quote End ---    Hello  The tool requires a device before I can create a new project.  I have no idea on which device I can use (basically I have no physical one). Could you give me a hint?

[Altera_Forum]

just pick one. You can set this to auto, and in theory it can pick a device for you. The synthesis is different for each device family. 

But usually you have an idea what device you're using before you start - based on factors such as boards available, cost, IO requirements etc.

[Altera_Forum]

--- Quote Start ---  just pick one. You can set this to auto, and in theory it can pick a device for you. The synthesis is different for each device family. But usually you have an idea what device you're using before you start - based on factors such as boards available, cost, IO requirements etc.  --- Quote End ---    Thank you very much  Now I can compile and use RTL Viewer to see. But when I use State Machine Viewer, it showed nothing.  Do you have any idea about this?

[Altera_Forum]

Maybe it didnt recognise a state machine. 

Post your code.

[Altera_Forum]

Hello, 

 Attached is my code

[Altera_Forum]

Usually, for a state machine, you would make the state a signal rather than variable, as well as leaving it as an enumerated type. 

 is there what you expect in the RTL diagram?

[Altera_Forum]

Actually, this code was not written by me, so I do not understand it's original purpose. 

 Maybe I am not an expert in model checking, but I think every piece of code can be converted to one (or more) corresponding state machine. Of course, this state machine may be a useless and ugly one, but valid