Hello dear community,
I am currently working on a project using a licensed IP (JESD204B) controlled through HPS that I didn't buy yet, but I do have the evaluation IP. This leads to get a time limited compiled FPGA project (.sof) and a constraint to programm only via Quartus, not via the SD card, since we need to keep the usb blaster connection.
So this brings a question, how am I supposed to test the HPS to FPGA bridges, and the project as a whole since the Linux will inevitably freeze while I'm programming FPGA with .sof ?
Does this means I have to debug FPGA on one hand, and HPS on the other hand ?
I may not understand correctly the part of you question, would like to clarify with you on that.
You mentioned that the Linux freeze when you are programming the QSPI?
What is the scenario that when freezing happened?
This only happened when you work with that particular IP?
What type of file that you are programming into the board(etc .sof)?
Thank you for your answer, in deed let me clarify.
I want to program my FPGA (5CSXFC6D6F31C6N) with a ".sof" compiled verilog project. This project includes HPS IP from qsys and other FPGA IPs, in particular a JESD204B IP which requires a license.
This means that my .sof project is time limited because I only have an evaluation license of the JESD204B IP.
So the only way to program the FPGA is through the programmer and usb blaster connexion, I cannot convert .sof into .rbf since time limited won't allow it.
This is problematic since in this post link it is mentionned that you cannot at the same time program FPGA with .sof and expect the linux to keep running, or at least it is not guaranteed.
In my case, freezing means I don't have any control over the Linux through putty for instance (serial or ssh).
So I wonder if there is a proper way to program FPGA through the programmer and to ensure the OS functionning without rebooting ?
The Linux will freeze and required a re-boot if your system is accessing the design content in the FPGA during runtime while you are trying to reprogram the content in FPGA.
You can avoid that by making sure that your system is not accessing the FPGA when you are trying to re-program it during runtime.
Due to the time limit for the evaluation IP which leads to your problem, I suggest you can try contact the sale personal about your issue to further query any other options that might work for your case.