How to use ddr2 sram high performance controller

[Altera_Forum]

Hi,I want to use ddr2 sdram in sopc. 

But I meet trouble. This is my project picture. Dose anyone have a example?if so,please give me a example,thanks.

[Altera_Forum]

That's a strange one, it looks like the span of the timer is expanding during generation. Typically this only happens when you hook up a master wider than a native slave. The Nios II data master is twice the width of the timer slave port so even though the timer takes up 16 bytes it's span will get promoted to 32 bytes which you can see in SOPC Builder. Try putting the PIO and CPU on the same clock domain as everything else in your system to avoid having clock crossing adapters dropped down into your system. 

 If that doesn't solve the problem try putting the memory at 0x0 and then place the peripherals far apart like 0x04000000, 0x04001000, 0x04002000  *edit: Which timer configuration are you using? Recently 64-bit support was added which causes the address span to double.

[Altera_Forum]

thank you for reply.The timer is 32bit.If I remove the timer,the problem remains. 

But if I remove two of then,the problem disappear. In my opinion,this problem is caused by ddr2 sdram.If I replace the ddr2 with onchip memory.the problem will also disappear. My English is poor,sorry.

[Altera_Forum]

I know the reason.Becase the ddr2 local width is 64bit. 

I don't konw if the ddr2 sdram can connect to the cpu directly.

[Altera_Forum]

That should have worked. The SDRAM controller exposes byte enables so everything should have mapped correctly. 

 Here is another thing to try, place everything except the SDRAM controller behind a pipeline bridge and then connect the bridge to the CPU.

[Altera_Forum]

Hi,badoman,I did that according to your advice,but the error remains. 

However,when I connect the ddr2 sdram to the pipeline bridge and other to cpu directly,error don't remains no longer.And then,the hardware can't work. So I want to konw whether this is right.

[Altera_Forum]

I think I have a hunch what is happening here but it'll be really tricky to explain. I think you are seeing a side effect of native addressing since the SDRAM in your system 64 bits wide. 

 How wide is the memory interface (between the FPGA and SDRAM), what is the local burst length, and are you using the SDRAM in half or full rate? I'm thinking a 32-bit pipeline bridge between the CPU and SDRAM controller will fix this but I'm not 100% certain of that.