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How to use only one channel on ADC port Max10

EEren
Novice
911 Views

I have an ADC core

component adc_qsys is
	port (
		adc_1_command_valid          : in  std_logic                     := '0';             --  adc_1_command.valid
		adc_1_command_channel        : in  std_logic_vector(4 downto 0)  := (others => '0'); --               .channel
		adc_1_command_startofpacket  : in  std_logic                     := '0';             --               .startofpacket
		adc_1_command_endofpacket    : in  std_logic                     := '0';             --               .endofpacket
		adc_1_command_ready          : out std_logic;                                        --               .ready
		adc_1_response_valid         : out std_logic;                                        -- adc_1_response.valid
		adc_1_response_channel       : out std_logic_vector(4 downto 0);                     --               .channel
		adc_1_response_data          : out std_logic_vector(11 downto 0);                    --               .data
		adc_1_response_startofpacket : out std_logic;                                        --               .startofpacket
		adc_1_response_endofpacket   : out std_logic;                                        --               .endofpacket
		clk_clk                      : in  std_logic                     := '0';             --            clk.clk
		reset_reset_n                : in  std_logic                     := '0'              --          reset.reset_n
	);
end component adc_qsys;


U_ADC_SYS : adc_qsys 
port map 
(
	clk_clk        => s_pll_clk_10M, 
	reset_reset_n  => '1', 
	
	adc_1_command_valid          => adc1_com_valid, 
	adc_1_command_channel        => adc1_com_channel, 
	adc_1_command_startofpacket  => adc1_com_startofpacket,
	adc_1_command_endofpacket    => adc1_com_endofpacket, 
	adc_1_command_ready          => adc1_com_ready,
	adc_1_response_valid         => adc1_resp_valid,
	adc_1_response_channel       => adc1_resp_channel,
	adc_1_response_data          => adc1_resp_data, 
	adc_1_response_startofpacket => adc1_resp_startofpacket,
	adc_1_response_endofpacket   => adc1_resp_endofpacket
);

When I used the whole port ADC1_IN1 - ADC1_IN8 was no problem.

Now I want to use only one channel - ADC1_IN1 so I set only CH1 active in the core.

adc.png

However I get the errors while compiling

 

Error (176310): Can't place multiple pins assigned to pin location Pin_7 (IOPAD_X0_Y37_N21)
Info (176311): Pin LED_CMD[5] is assigned to pin location Pin_7 (IOPAD_X0_Y37_N21)
Info (176311): Pin ~ALTERA_ADC1IN2~ is assigned to pin location Pin_7 (IOPAD_X0_Y37_N21)
Error (176310): Can't place multiple pins assigned to pin location Pin_8 (IOPAD_X0_Y36_N14)
Info (176311): Pin LED_CMD[6] is assigned to pin location Pin_8 (IOPAD_X0_Y36_N14)
Info (176311): Pin ~ALTERA_ADC1IN3~ is assigned to pin location Pin_8 (IOPAD_X0_Y36_N14)
Error (176310): Can't place multiple pins assigned to pin location Pin_10 (IOPAD_X0_Y36_N21)
Info (176311): Pin LED_CMD[7] is assigned to pin location Pin_10 (IOPAD_X0_Y36_N21)
Info (176311): Pin ~ALTERA_ADC1IN4~ is assigned to pin location Pin_10 (IOPAD_X0_Y36_N21)
Error (176310): Can't place multiple pins assigned to pin location Pin_11 (IOPAD_X0_Y35_N14)
Info (176311): Pin LED_CMD[8] is assigned to pin location Pin_11 (IOPAD_X0_Y35_N14)
Info (176311): Pin ~ALTERA_ADC1IN5~ is assigned to pin location Pin_11 (IOPAD_X0_Y35_N14)
Error (176310): Can't place multiple pins assigned to pin location Pin_12 (IOPAD_X0_Y35_N21)
Info (176311): Pin LED_CMD[9] is assigned to pin location Pin_12 (IOPAD_X0_Y35_N21)
Info (176311): Pin ~ALTERA_ADC1IN6~ is assigned to pin location Pin_12 (IOPAD_X0_Y35_N21)
Error (176310): Can't place multiple pins assigned to pin location Pin_13 (IOPAD_X0_Y34_N14)
Info (176311): Pin LED_TEST is assigned to pin location Pin_13 (IOPAD_X0_Y34_N14)
Info (176311): Pin ~ALTERA_ADC1IN7~ is assigned to pin location Pin_13 (IOPAD_X0_Y34_N14)
Error (176310): Can't place multiple pins assigned to pin location Pin_14 (IOPAD_X0_Y34_N21)
Info (176311): Pin LED_FLTn is assigned to pin location Pin_14 (IOPAD_X0_Y34_N21)
Info (176311): Pin ~ALTERA_ADC1IN8~ is assigned to pin location Pin_14 (IOPAD_X0_Y34_N21)

 

How can I resolve the problem?

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Farabi
Employee
878 Views

Hi, 

 

You may see this pin placement error in the Quartus® II software if you have enabled the Passive Serial (PS)configuration scheme and assigned the DCLK pin as a regular I/O pin. You can only assign the DCLK pin as a regular I/O pin if you selected the Active Serial (AS) configuration scheme.  When the Passive Serial configuration scheme is selected, the DCLK pin can only be used as a programming pin.

Resolution

Change to the Active Serial configuration scheme or remove the user signal location assignment to the DCLK pin.

 

please refer pin connection guideline. 

 

regards,
Farabi

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EEren
Novice
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Sorry, I failed to understand. How DCLK pin related to ADC pins? And where do I change this configuration to Active Serial?

 

As I see in MAX10 Configuration Scheme may be only - Internal Configuration. It's an on board flash in the device.

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EEren
Novice
867 Views

Well... I found the answer - If you use bank 1A for ADC, you cannot use the bank for GPIO.

 

At least something stays rock solid - the support is traditionally lame on the forum.

 
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Farabi
Employee
840 Views

Hi, 

 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

regards,

Farabi

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