How to write DATA to RAM and Internal Memory in FLEX10K

[Altera_Forum]

Dear all, 

 I am in the middle of a project and have come across a glitch at the moment. One of the core aspects of this project is to write the data received from encoders or LCD to the internal memory provided within the FLEX10K. I have been searching and have found that the FLEX10 has 2KB of memory. In the FLEX10K there are 8 EAB's each with a capacity of 2048 bits. How can I write to a specific spot in memory.  From my understanding, each one of those bits in the EAB should have an address associated with it. My question is how do I decide which address I can write to and how do I do that in VHDL.   From my research I came across people using *.mif and *.hex files but I do not see how it can be used since it does not provide an address. I also saw the Megawizard Plug-In manager for several RAM and ROM schematics but I still am not sure how to implement it on the FLEX10K.  I appreciate all kinds of help.  Cheers

[Altera_Forum]

--- Quote Start ---  Dear all,  I am in the middle of a project and have come across a glitch at the moment. One of the core aspects of this project is to write the data received from encoders or LCD to the internal memory provided within the FLEX10K. I have been searching and have found that the FLEX10 has 2KB of memory. In the FLEX10K there are 8 EAB's each with a capacity of 2048 bits. How can I write to a specific spot in memory.  From my understanding, each one of those bits in the EAB should have an address associated with it. My question is how do I decide which address I can write to and how do I do that in VHDL.   From my research I came across people using *.mif and *.hex files but I do not see how it can be used since it does not provide an address. I also saw the Megawizard Plug-In manager for several RAM and ROM schematics but I still am not sure how to implement it on the FLEX10K.  I appreciate all kinds of help.  Cheers  --- Quote End ---     Hi Ali,  I would recommend to use the Quartus build-in Megawizard. The megawizard does not generate a schematic for the RAM. It will generate a Verilog or VHDL for the RAM. In the HDL file you will find the instanciated Memory function with all the choosen settings.Don't forget to set the FPGA family on the the first page!

[Altera_Forum]

Thanks very much for the reply. 

 I now have a few extra questions. What I would like to do is to have 21 bits of information in one row out of 256 columns. That 21 bits of information will comprise the outputs from three to four different locations. How am I able to work in away that I have have the bits in the order that I want them to be.  For example, one output is speed (being 5 bits for eg) and the other output is distance which will be (10 bits lets say). How am I able to combine those into 15 bits having the first 5 bits for speed and the last 10 bits for distance or vise versa. Is this even possible or should we have a different approach to what we're doing.   Thanks everybody!

[Altera_Forum]

--- Quote Start ---  Thanks very much for the reply.  I now have a few extra questions. What I would like to do is to have 21 bits of information in one row out of 256 columns. That 21 bits of information will comprise the outputs from three to four different locations. How am I able to work in away that I have have the bits in the order that I want them to be.  For example, one output is speed (being 5 bits for eg) and the other output is distance which will be (10 bits lets say). How am I able to combine those into 15 bits having the first 5 bits for speed and the last 10 bits for distance or vise versa. Is this even possible or should we have a different approach to what we're doing.   Thanks everybody!  --- Quote End ---    Hi Ali,  do you mean that you have to store 256 data words with 21bits each ?

[Altera_Forum]

I don't see the meaning of the data directly related to the way of storing it. The main restriction of storing different entities in a common RAM is that they share the addresses, that means, you can't access item 3 of data A and item 255 of data B simultanously.