Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19199 Discussions

I Have imported the correct libraries and still get an error.

Honored Contributor II

So i have this little piece of a datapath entity. 


library ieee; 

use ieee.std_logic_1164.all; 

use IEEE.std_logic_arith.all; 

use IEEE.std_logic_unsigned.all; 


entity Datapath is port ( 

R1, R2, E1, E2, E3, E4, E5: in std_logic; 

CLOCK_50: in std_logic; 

SEQIN,SQR: in std_logic_vector (9 downto 0); 

SW_erro, end_game, end_time, end_round: out std_logic; 

Smt: out std_logic_vector(3 downto 0); 

SmN: out std_logic_vector (3 downto 0); 

result: out std_logic_vector (7 downto 0) 



end Datapath; 


architecture arqdtp of Datapath is 

signal SmSwitches: std_logic_vector(2 downto 0); 

signal SeqRom, SeqSw: std_logic_vector(9 downto 0); 

signal SmT_in, SmN_in: std_logic_vector(3 downto 0); 

signal C: std_logic; 


-- Registrador e Somador: 

P1: process(CLOCK_50,R1) 


if (R1 = '1') then -- R1 Time reset  

Smt_in<= "0101"; 

elsif (CLOCK_50'event AND CLOCK_50 = '1') then  

if (E1 = '1') then 

Smt_in <= Smt_in - '1'; 

SmT <= SmT_in; 

end if; 

end if; 

end process; 


P2: process(CLOCK_50,R2) 


if (R2 = '1') then -- R2 reset Next round  

SmN_in<= "0000"; -- Soma Next round  

elsif (CLOCK_50'event AND CLOCK_50 = '1') then  

if (E3 = '1') then 

SmN_in <= SmN_in + '1'; 

SmN <= SmN_in; 

end if; 

end if; 

end process; 


-- Comparador: 

end_time <= '1' when (Smt_in = "0000") else '0'; 

end_round <= '1' when (SmN_in = "1010") else '0'; 

end_game <= '1' when (SeqSw = SeqRom)else '0'; 

SmSwitches <= (SEQIN(1)+SEQIN(2)+SEQIN(3)+SEQIN(4)+SEQIN(5)+SEQIN(6)+SEQIN(7)+SEQIN(8)+SEQIN(9)); -- For some reason it gives me the error here. 

SW_erro<= '1' when (SmSwitches > "0100") else '0';  


-- Sequencia secreta  

P3: process(CLOCK_50,E4) 


if (E4 = '1') then -- Sequencia do Jogo reset  

SeqSw<= "0000000000"; -- Sequencia 4 bits  

elsif (CLOCK_50'event AND CLOCK_50 = '1' and E2 = '1') then  

SeqRom <= SEQR; 

end if; 

end process; 


-- Sequencia escolhida  

P4: process(E5) 


if (E5 = '1') then -- Sequencia Escolhida reset  

SeqRom<= "0000000000"; -- Sequencia 10 bits 

C <= end_game; 

result <= ("16" * C) + ("10" - SmN); 

end if; 

end process; 

end arqdtp; 


and i am still getting: Error (10327): VHDL error at Datapath.vhd(53): can't determine definition of operator ""+"" -- found 0 possible definitions 

Can anyone please help me? It is urgent.
0 Kudos
2 Replies
Honored Contributor II



Go through the previous thread. 


1. Adding 9 1-bit data (SEQIN) and displaying the result in a 3-bit (SmSwitches), You required to use VHDL concatenation operator (&) is used to put a 0 in front/back of each of the 9 1-bit numbers before adding them. 

SmSwitches <= ("00"& SEQIN(1)+"00"& SEQIN(2)+"00"&SEQIN(3)+"00"&SEQIN(4)+"00"&SEQIN(5)+"00"&SEQIN(6)+"00"&SEQIN(7)+"00"&SEQIN(8)+"00"&SEQIN(9)); 

2. You can use numeric and unsigned library. 


Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 


Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Honored Contributor II

The SmSwitches signal is declared as a 3-bit vector. How are you trying to add or concatenate 9 bits into a 3-bit vector ? If you're trying to concatenate bits to form a 3-bit signal then you need to use the '&' operator.