Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

I/O Pin voltage

Altera_Forum
Honored Contributor II
‎05-11-2011 06:53 AM
1,124 Views

Hello, 

I am trying to design a simple multiplexer using the Cyclone III FPGA on the DE0 board. I am using the PLL to divide the 50MHz on board clock down to the appropriate speed. However whenever I try to put a signal out to one of the I/O pins, it is only about 20mV peak to peak. I understand the pins on the DE0 board should put out 3.3V. I have the pins assigned to the 3.3V standard in the Quartus II pin planner, but it doesn't seem to make any difference. Any help would be appreciated.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎05-13-2011 05:01 AM
400 Views

You can try the following steps to set the output voltage: 

Menu : Assignments -> Device -> Device and Pin Options  

In Voltage Tab you can choose 3.3V LVTTL for Default I/O Standard.  

Then don't forget compile your project.  

 

I also use DE0 board and every time I use the default voltage. 

 

I hope it can help you. 

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.