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Honored Contributor I
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I/O Restriction Rules

Hi community, 

 

I have a question about the I/O Restriction Rules in m10_sidg.pdf p.7 table 2. 

I am a bit confused. I know my ICs (MAX9275) are using the LVCMOS input and outputs but will run with 1.8V instead of 2.5V. So, is there any recommendation for this standard or is there only one for the 2.5V case? 

Important info probably: These pins are just parallel data inputs and outputs. No differential pairs RX/TX. So am I right, when I suggest that this standard doesn't count for simple data in and outs, so that I can use up to 100% at each bank? 

 

Or simply asked: 

Does these restrictions only count, if I am using diff pairs RX/TX routed to the FPGA bank?  

For simple parallel data lines these restrictions doesn't count. Right? 

OR, are there any restrictions for parallel data pins at the FPGA, especially for the maximum number of these parallel data pins in one bank. 

 

Hopefully someone can help me a bit. 

 

 

Thanks in advance. 

Jérôme 

 

edt.: Ok, I see. Just didn't read the word "recommended". So I can use more than 65%. Thanks mates ;)
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