I_PIN_PERST_N signal is not assignable in Agilex 7

[Finees]

Hi

I am building a PCIe controller on Agilex 7 (AGIB027R31B2E3). I want to assign the I_PIN_PERST_N signal in bank 13C. In the Pin Planner, I try to assign pin Y21 as the PERST_N signal, but I get a message that the pin is not assignable. But if I don't assign the pin, I get the following Critical Warning: "There is no accurate pin location assignment(s) for 1 of the 693 total pins. To see the pin list, refer to the I/O assignment warnings table in the installer report."
I have checked the pins and banks that the signal can be assigned to (AA54 on bank 12C, CN20 on bank 13A, Y21 on bank 13C and CT57 on bank 14A) and have configured this pin as LVCMOS 1.8V and put a pull-up resistor on it (https://www.intel.com/content/www/us/en/docs/programmable/683112/current/f-tile-transceiver-pins.html).
Does anyone know how to solve this issue?

[wchiah · Accepted solution]

Hi,

In the Pin Planner, I try to assign pin Y21 as the PERST_N signal, but I get a message that the pin is not assignable. 

>> if you assign the pin based on the example design, did you see any error ?

>> is there any specific reason you change the pin location ?

But if I don't assign the pin, I get the following Critical Warning: "There is no accurate pin location assignment(s) for 1 of the 693 total pins. To see the pin list, refer to the I/O assignment warnings table in the installer report."

>> According to the user guide , If the F-tile is unused, or the F-tile is used but PCI Express* is unused, tie to GND.

>> Did you try to Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to the 1.8-V input of each F-tile transceiver that is used on the board. Provide a 1.8-V pull-up resistor for this input pin as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

>> PERST# should be connected between the host slot and our device as shown in our dev kit schematic:

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/agilex/f-fpga/agilex-f-fpga-dk-2v-es.pdf

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[Finees]

Hi
Sorry for delay. It was useful the information that you provided me. I provided a 1.8V pull-up resistor in the pin perst_n.

I have no further questions.
Thank you

[wchiah]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

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Regards,

Wincent_Intel