I am seeing the following error when running Timing Analysis for Stratix 10. Error: LVDS SDC cannot find IOPLL. Ensure IOPLL SDC is listed before LVDS...

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

I am seeing the following error when running Timing Analysis for Stratix 10. Error: LVDS SDC cannot find IOPLL. Ensure IOPLL SDC is listed before LVDS SDC in qsf.

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I tried implementing the workaround mentioned in the following link, but it does not solve the problem.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2019/error--lvds-sdc-cannot-find-iopll--ensure-iopll-sdc-is-listed-be.html

I am using Quartus Version 19.1.0 Build 240 03/26/2019 SJ Pro Edition.

I have installed patch 0.19 as mentioned in the above link.

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