# ** Error (suppressible): (vsim-SDF-3196) Failed to find SDF file "Ass1_vhd.sdo".# vsim -novopt -c -t 1ps -sdfmax Ass1_vhd_vec_tst/i1=Ass1_vhd.sdo -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Ass1_vhd_vec_tst
# Error loading design
It seems that you are missing the .sdo file.
Note that: Gate-level timing simulation of an entire design can be slow and should be avoided.
Gate-level timing simulation is supported only for the Arria II GX/GZ,Cyclone IV, MAX
II, MAX V, and Stratix IV device families.. Use Timing Analyzer static timing analysis
rather than gate-level timing simulation.