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Beginner
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I instantiaze a pll with 4 output clock,but when I use Derive PLL Clocks command in Timing Analyzer, it only derive two generated clock?

altpll1 altpll1_inst (

   .inclk0 ( chip_clk ),//20Mhz

   .c0 ( sys_clk ), //400Mhz

   .c1 ( uart_clk ), //25Mhz

   .c2 ( clk_50M ), //50Mhz

   .c3 ( clk_30M ),//30Mhz

   .locked ( locked_sig )

   );

according the route " Timing Analyzer->constraints->Create Generated clock "

to open "Create Generated Clock" window ,

11111.png

and the open the ->source window

11112.png

there are just the output clock clk[2] and clk[3] of the pll,where is the clk[0] and clk[1] of the pll?

by the way the ouput clk[0] is 400Mhz, and the ouput clk[1] is 25Mhz ,

and after run the create generate clock command ,there are only

the generate clock clk[2] ,cllk[3], what is the reason ?

 

 

 

 

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3 Replies
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Employee
4 Views

Hi ,

When I made a simple PLL and try to put the list fro the name finder , I can see all the out put from the PLL . May I know is that is a problem for you . The same is not view by you

 

Regards,

Rahul S

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Beginner
4 Views

oh, perhaps because I only do synthesis step, and do not do the fitter step

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Retired Employee
4 Views

And you don't even need to create the generated clocks like this. Just put derive_pll_clocks -create_base_clocks in your .sdc file to automatically create all the clock constraints from the PLL IP.

 

#iwork4intel

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