altpll1 altpll1_inst (
.inclk0 ( chip_clk ),//20Mhz
.c0 ( sys_clk ), //400Mhz
.c1 ( uart_clk ), //25Mhz
.c2 ( clk_50M ), //50Mhz
.c3 ( clk_30M ),//30Mhz
.locked ( locked_sig )
according the route " Timing Analyzer->constraints->Create Generated clock "
to open "Create Generated Clock" window ,
and the open the ->source window
there are just the output clock clk and clk of the pll,where is the clk and clk of the pll?
by the way the ouput clk is 400Mhz, and the ouput clk is 25Mhz ,
and after run the create generate clock command ,there are only
the generate clock clk ,cllk, what is the reason ?
When I made a simple PLL and try to put the list fro the name finder , I can see all the out put from the PLL . May I know is that is a problem for you . The same is not view by you
And you don't even need to create the generated clocks like this. Just put derive_pll_clocks -create_base_clocks in your .sdc file to automatically create all the clock constraints from the PLL IP.