I put the DDR3 controller on a 10M25DAF484 device, for that application I can use just one DQ block so I'm able to use only the bank6 but the RUP and RDN are on the bank5. Is there a way to put all the DDR signal on the bank6 in order to recover bank5?

[NurAida_A_Intel]

Hi Sir,

As per my understanding, you want to place all your DDR signal in Bank 6 and move the RUP/RDN from Bank 5 to Bank 6 as well. Is this correct? Please let me know if I understand this correctly.

If my assumption correct, kindly please refer to below explanation about the RUP/RDN placement :

• Some DQS or DQ pins are dual purpose and can also be required as RUP, RDN, or configuration pins. A DQS group is lost if you use these pins for configuration or as RUP or RDN pins for calibrated OCT.
• You need to pick RUP and RDN pins in a DQS group that is not used for memory interface purposes.
• You may need to place the DQS and DQ pins manually if you place the RUP and RDN pins in the same DQS group pins. 

Regards,

Aida

[PCiam]

Hi Aida, you are right. My goal is to place all the DDR signals on bank 6 in order to use bank 5 with a different VCCIO. The idea is to use the DQS1 group (pin M15, M14 and so on) and additional pin for the control signals and addresses. All the DQS2 group signals (K14, K15 ...) are free so, if I understood well, I can move the RUP and RDN signals from bank 5 in a couple of pin of DQS2 group and ay yhe same time I'll loose the DQS2 functionalities. Is this correct. I'll send you a possible pinout in order to check if I understood well the constrain, in that file the orange row are referred to DQS2 signal group and the green row are not usable. I thank you very much for the support. Best regards Pietro Ciammaichella Il 11/05/2020 06:55 Intel Forums ha scritto: Links:

[NurAida_A_Intel]

Hi Sir,

I can move the RUP and RDN signals from bank 5 in a couple of pin of DQS2 group and ay yhe same time I'll loose the DQS2 functionalities. Is this correct. --> Yes, you're right.

Please also take note on the following impacts on your DQS groups when the RUP and RDN pins in devices being used as DQ and DQS pins when they are not used to support OCT:

1) If the RUP and RDN pins are part of a ×4 DQS group, you cannot use that DQS group in ×4 mode.

2) If the RUP and RDN pins are part of a ×8 DQS group, you can only use this group in ×8 mode if any of the following conditions apply:

• You are not using DM or BWSn pins.
• You are not using a ×8 or ×9 QDR II SRAM device, as the RUP and RDN pins may have dual purpose function as the CQn pins. In this case, pick different pin locations for RUP and RDN pins, to avoid conflict with memory interface pin placement. You have the choice of placing the RUP and RDN pins in the same bank as the write data pin group or address and command pin group.
• You are not using complementary or differential DQS pins. 

Thanks

Regards,

Aida