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I've a problem with PCIe in Arria10. Сoreclkout_hip = 0!

VMich4
Beginner
438 Views

We have developed a module with installed FPGA Arria 10. FPGA - 10Ax022E4F29i3. In the project we use IPCore Pcie (HardIP). Refclk (100MHz) is detected inside FPGA (SignalTap "sees"). But on the output IPCore:

coreclkout_hip = 0; (!!!)

rx_is_lockedtoref = 0;

rx_is_lockedtodata = 0;

reset_status = 1;

But

serdes_pll_locked = 1.

So far I have not had such problems with HardIP PCIe.

Сoreclkout_hip was always available.

 

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4 Replies
AndyN
New Contributor I
148 Views

Sounds like you're just stuck in reset. What're the npor and pin_perst inputs to the IP doing?

BoonT_Intel
Moderator
148 Views

AndyN, thanks for help.

 

Other than reset, what is the sampling clock that you used for signaltap (STP)? If the sampling clock is slower or same frequency compare to the coreclkout_hip. Then you might unable to see it toggling in STP.

VMich4
Beginner
148 Views

we tried different varients for npor and perst... it doesn't works. And this poject on Altera KIT (Arria 10 GX115) works!

 

STP used diff. freq - 100 ref_clk from input, 62,5 MHZ from other pin. nothing.... And reset_status = 1!!

BoonT_Intel
Moderator
148 Views

Hi sir,

Can you please elaborate on this sentence?

 

STP used diff. freq - 100 ref_clk from input, 62,5 MHZ from other pin. nothing.... And reset_status = 1!!

 

Does it mean ref clock is 100Mhz, other pin with 62.5Mhz is for which signal? And 'nothing' is referring to what?

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