I have an FPGA that is running components that expose it as an SPI slave. The other master is a Raspberi pi. I am trying to write SDC constraints on SPI_SCLK and do not know where to start. I have read a lot about time quest, launch, latch and have the basics. I just don't know what to describe the spi_clock as. Is it a base or virtual clock? I know there might have to be input/output delays on the paths, or multicycles, but how do I describe the clock. Base, virtual, ??? Thanks, I am a hobbiest
Thank you, I had once looked at the above link. That is not my exact situation. In my case, the clock is generated in the raspberry pi and delivered to the FPGA. The FPGA is acting as a slave in my design. SCLK needs constraining in the FPGA. In the above link, the FPGA is acting a master. In the above link, they used create_generated_clock to define the spi clock. I do not think that is the right command when the clock is generated in the raspberry pi. I suspect I need to use a virtual clock for this case, please elaborate how to constrain the SPI click in the FPGA. Lets assume that the spi clock is 1 MHz, when data is sent.