I2C master ip: How/where are the bidirectional open drain line buffers?

[Rodo]

Hi all,

This is for Quartus Lite 21.1 (free version), MAX10 (10M08) and NIOS II, BeMicro MAX10 development kit. I want to add an I2C core to connect the MAX10 to the ADT7420 digital temperature sensor on the board. Then use NIOS/Eclipse to write code, read the temperature and display it in a character LCD that it is already working.

I found "Avalon I2C (Master) Intel FPGA IP" in the ip catalog. There are only two parameters to set. The first one has to do with command fifo, data fifo and the options are "Avalon-MM Slave" or "Avalon-ST". I thought I don't want "Avalon-ST" (Streaming?) but that leaves the other option which is a slave? I picked "Avalon-MM Slave" because I saw it in a post (link below). I want the NIOS to be the master and the sensor to be the slave. The second parameter is the depth of fifo. I left that set as 4.

The Intel Embedded Peripherals IP User Guide (chapter 15, figure 52, pages 180-181) says:

15.7.3. I2C Serial Interface Connection
The core provides four ports for I2C serial connections. For external I2C serial connections, both sda_in and sda_oe are connected to a bidirectional open drain I2C data line buffer. Both scl_in and scl_oe are connected to another bidirectional open drain I2C clock line buffer. It is recommended to use the I/O IP core to generate the bidirectional open drain buffer. You can then instantiates the generated buffer primitives from the IP core into their system top level design file.

I can add the I2C core in platform designer and make its connections except that I don't know what to do with sda_in,sda_oe and scl_in, scl_oe. I don't see the "recommended" I/O IP core in the catalog. I tried a PIO core but that seems wrong.

I read the sample code in verilog shown in page 181 (below figure 52) but I don't understand what to do with it. My verilog is old and rusty. I haven't done anything in verilog to build the system so far. Is that the way to do this?

I found this post (link below) but I don't see the I/O IP core in platform designer:
https://community.intel.com/t5/Nios-II-Embedded-Design-Suite/I2C-master-with-NIOS-2/td-p/1245961

Any help would be appreciated. Thanks

[Rodo]

For anyone new (like me) interested in this: There seem to be two IP catalogs. One in Quartus. Press Alt-7 if you don't see it. And another inside the platform designer. The GPIO Lite IP core that has the tri-state buffer is on the Quartus IP catalog. For me, it doesn't show up in the platform designer IP catalog. Information on the GPIO Lite IP core  is in "Intel® MAX® 10 General Purpose I/O User Guide" Chapter 4. Enjoy.

[EricMunYew_C_Intel]

You may refer to below method.

https://community.intel.com/t5/FPGA-Wiki/I2C-OpenCores/ta-p/735640

[EricMunYew_C_Intel]

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