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I2c through FPGA not working on Cyclone V SoC Terasic DE1SoC board

Honored Contributor II


I have connected the external I2C device through FPGA fabric to GPIO pins on the board. I'm using I2C1 (0xffco5000) I have created new preloader, uboot and linux distro, rbf and dtb file, etc..., everything that is needed i guess.  

Nevertheless none of the software is able to interface correctly with i2c devices (i.e. 24AA02 EEPROM). 

signals are routed through tri-state buffers (see attachments). I can see the SDA pin is going low for about 1us or less (measured on signaltap and external scope), but with no following scl signal present. 


I can see that peripherial is configured well on linux using commands like:# busybox devmem 0xffc05000 

0x00000065# busybox devmem 0xffc05004 

0x00000050# busybox devmem 0xffc05008 

0x00000055# busybox devmem 0xffc0500c 

0x00000000# busybox devmem 0xffc05010 

0x00000000# busybox devmem 0xffc05014 

0x000001AB# busybox devmem 0xffc05018 

0x000001F3# busybox devmem 0xffc0501c 

0x00000057# busybox devmem 0xffc05020 

0x0000009F# busybox devmem 0xffc05024 

0x00000000# busybox devmem 0xffc05028 



interaction with i2cdetect -y 0 gives 

i2c_designware ffc05000.i2c: i2c_dw_handle_tx_abort: lost arbitration 


uboot - trying to read MAC address also fails what is predictable from signal analysis with scope mentioned at the beginning. 

regarding uboot - I have changed header files containing definitions of I2C controller address to match I2C1 controller. 

i2c probe in uboot - gives series of low impulses about 75us long on SDA, nothing on SCL. 


Does anybody can help me, please?
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4 Replies
Honored Contributor II

OK, So the problem was trivial, the i2c clock was connected to SPI clock :). I don't know how much time i have spent on this...

Honored Contributor II

Hi Settem, did you start with the GHRD project? I'm wondering if i2c would work with just changing the device tree and keeping the preloader and u-boot the same. I'm using GHRD as my base project. I want to connect an external device through the fpga fabric using hps i2c. My current problem is that I don't see any address returned from i2cdetect. 

If you could share your project or device tree that would be great.
Honored Contributor II

Dear Nalkhateeb, 

no, I'm not starting with GHRD. I like using schematic as a top level entity and all examples are top level textual. 

Preloader is configuring registers in processor, so probably without changing it, it wouldn't work. If You want to use peripherals via FPGA fabric, the internal mux register needs to be set accordingly by preloader. 

You can doublecheck see how this registers are set with devmem linux command. 

Next thing is the correct connection of IOs to signals in QSys entity. I had connection problems probably because I have changed version of Quartus in the meantime an it was incompatible. As far as i remember, in older versions I2C could be master only/slave only/full, and now it can be only full. Pay attention to connectionss. 

I could also recommend to update timing parameters of i2c driver in devicetree. Default timing parameters failed for some of my slave devices. Some worked, some not. Some slave device was unable to signal the ACK. It looked like HPS was not issuing High-Z to pin in correct time. Here is my i2c device tree entry with overwritten timings that worked for me: 

hps_i2c1: i2c@0xffc05000 { compatible = "snps,designware-i2c-17.0", "snps,designware-i2c"; reg = <0xffc05000 0x00000100>; interrupt-parent = <&hps_arm_gic_0>; interrupts = <0 159 4>; clocks = <&l4_sp_clk>; emptyfifo_hold_master = <1>; /* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */ status = "okay"; /* embeddedsw.dts.params.status type STRING */ clock-frequency = <100000>; i2c-sda-hold-time-ns = <100>; i2c-sda-falling-time-ns = <100>; i2c-scl-falling-time-ns = <300>; }; //end i2c@0xffc05000 (hps_i2c1)
Honored Contributor II

Thanks for sharing. I need to do more tests but things seem to be working now.